Built-in capabilities make it easy to meet the toughest timing requirements for industry-standard and custom protocols, while supporting multiple electrical standards in the same device with 30 individually configurable I/O banks.

• Design with PCI®, RapidIO™, XSBI, SPI4.2, and more
• Configure I/Os to support HSTL, LVDS (SDR and DDR), and more, at voltages from 1.0V to 2.5V
• Built-in write leveling support for DDR3 1066 memory
• Simplify board design with built-in I/O delay circuits that compensate for unequal trace lengths with flexible per-bit deskew
• Synchronize incoming data to FPGA internal clock with built-in Serializer/ Deserializer
• Adaptive delay setting recalibrates automatically to compensate for changing operating conditions
• New performance path clocking networks provide dedicated paths to reduce jitter for off-chip clocking
• Three-statable I/O reduces power for memory interfaces
• Digitally-Controlled Impedance (DCI) with on-chip active I/O termination reduces component count, saves board space, and simplifies board design