Second generation ExpressFabric technology employs 6-input look-up tables (LUT) for higher performance through reduced number of logic levels, reduced routing, and lower fanout. For additional performance gains, Xilinx doubled the number of flip-flops associated with each LUT to better support pipelining of high-speed designs.

• 40nm triple-oxide process delivers one speed-grade higher performance, 50% lower power than previous generation
• Second-generation six-input look-up table (LUT) architecture enhances pipelining with highest flip-flop:LUT ratio
• Flexible LUTs are configurable as logic, distributed RAM (64 bits per LUT / 256 bits per CLB) or shift registers
• Second-generation diagonally symmetric interconnect enables shortest, fastest routing
• From 74,500 to 758,800 logic cells for system-level integration