Virtex-6 FPGAs offer up to 38Mbits of integrated block RAM for buffering and storing data on chip. Flexible block RAM can be configured as two 18Kb blocks or a single 36Kb block, true dual-port, simple dual-port, and FIFO, and offers independent read and write port width configuration. Achieve 600MHz operation using optional pipeline capability. Built-in cascade logic makes it possible to create a 64k x 1 memory from two 32k x 1 block RAM configurations.

• Split into two 18 Kbit blocks to double Block RAM bandwidth
• Configure block RAM as multi-rate FIFO
• Built-in 64-bit error-correcting code (ECC) function for high-reliability systems
• Automatic power conservation circuitry