New mixed-mode clock managers (MMCM) in Virtex-6 FPGAs deliver the benefits of flexible, precise clock synthesis, phase shifting, and jitter filtering provided by the DCM and PLL circuits in the device's clock management tiles (CMT). Enhanced clock distribution networks employ new mid-point buffering to reduce skew.

• New PLL-based mixed-mode clock managers (MMCM) for lowest jitter, jitter filtering
• Improved frequency synthesis offers 8x finer control
• Same fine phase control as provided by Virtex-5 DCM technology
• 18 MMCMs provide precise phase control of less than 30ps for better design margin
• Differential global and regional clocking ensures low skew and jitter
• Mid-point buffering reduce skew and jitter in on-chip clock network