Achieve 1,000GMACS performance using DSP48E1 slices to build efficient hardware implementations of filters that leverage the parallelism inherent in the FPGA architecture.

• Increased DSP resources in all devices; up to 2,016 slices in a Virtex-6 SX475T FPGA
• Enhanced architecture with a 25 x 18 multiplier, 48-bit adder, and 48-bit accumulator (cascadable to 96 bits) enables single and double-precision floating-point math and high precision filters with fewer slices
• New integrated pre-adder implements more efficient, higher-performance symmetric and polyphase filters
• Support for pattern detection, convergent rounding, and underflow/overflow detection for saturation arithmetic
• Over 40 dynamically controlled operating modes including multiplier, multiplier-accumulator, multiplier-adder/subtractor, three input adder, barrel shifter, wide bus multiplexers, wide counters, and comparators
• Low power consumption: each DSP48E1 slice draws only 1.09mW/100MHz at a 38% toggle rate, a 20% reduction from previous-generation slices