Minimize design risk with integrated PCIe interface blocks for building next-generation graphics, storage, networking, and I/O devices. The PCI Express block in Virtex-6 FPGAs implements transaction layer, data link layer, and physical layer functions to provide complete PCI Express endpoint and root-port functionality with minimal FPGA logic utilization.

• PCI SIG-verified Gen1 and Gen2 compliance (on integrators list)
• Works with GTX transceivers to deliver PCIe endpoint and root port function
• Built-in hard IP frees user logic resources and reduces power
• Multiple PCIe blocks for increased bandwidth, multiple functions, or simultaneous implementation of endpoint and root port support in a single FPGA
• Preserve software investment and extend infrastructure life with scaleable bandwidth (x1, x2, x4, x8 at Gen1 and Gen2 data rates)
• Re-target designs to larger FPGAs without changing your PCIe interface implementation as your project evolves
• PCI Express ( PCIE )