Configurable logic blocks (CLB)
CLB architecture provides wider functionality and less logic levels resulting in higher performance.
- Four slices per CLB - two each for memory and logic functions.
- Wide-input functions - 16:1 mux in one CLB
- Fast arithmetic functions - two look-ahead carry chains per CLB column
- Four cascadable 16-bit addressable shift registers
- Two slices can be configured as distributed memory