Multi level memory architecture
Four level memory architecture (PDF) provides the optimal granularity and efficient area utilization.
- Up to 520 Kb distributed SelectRAM™+ memory
- Each LUT works as a single-port or dual-port RAM/ROM
- LUTs can be cascaded to build larger memories
- Flexible memory for FIFOs, and buffers
- Up to 1.87 Mb embedded block RAM
- Up to 104 blocks of synchronous 18 Kb block RAM can be cascaded
- Each 18 Kb block can be configured as a single/dual-port RAM
- Supports multiple aspect ratios, data-width conversion and parity
- Up to 16 Mb of integrated Flash memory
- System flexibility with up to 11Mb of on-chip user Flash
- Single-chip solution for failsafe field upgradeability using MultiBoot feature
- New benchmark in non-volatile FPGA market for retention and cycling
- Popular low cost external memory
- Connects low cost memories via interfaces such as HSTL and SSTL
- Large system memory requirements