Co-Simulate and Debug
Co-Debug
Xilinx supports Hardware IP (on programmable logic) and processor software co-debug through the collaboration of two tools: Chipscope™ Pro which inserts logic analyzer and system analyzer cores directly into designs; and Xilinx Software Development Kit (SDK) whose integrated debugger allows developers to set breakpoints or watchpoints, step through program execution, view the program variables and stack, and view the contents of the memory in the system.
Co-Simulate
High-Level Functional Models
The Zynq™-7000 All Programmable SoC (AP SoC) Virtual Platform by Cadence provides functional, Transaction Level Models of the Zynq-7000 AP SoC processing subsystem as well as the tools to extend the off-the-shelf model with custom IP cores instantiated within the programmable logic. The virtual platform is binary compatible with physical hardware so that SW code compiled for the Virtual Platform will run on the real hardware too. Offering full visibility and control of every device and time itself, the virtual platform , and it provides debug and development capabilities that are unmatched by physical hardware to speed software development, integration and test.
HDL, Verilog, etc.
Programmable logic IP, for which RTL or HDL already exists can be integrated with the Zynq-7000 AP SoC functional model through licensed access to Cadence Incisive Enterprise Simulator or Cadence Palladium series product.
In ISE® Design Suite 14.2, Xilinx provides co-simulation tools will enable developers to mix of IP cores within Xilinx iSim, simultaneous with direct execution of code on the Zynq-7000 AP SoC ARM cores. Such capability will further Xilinx's off-the-shelf capabilities for mixed environments of physical hardware and HDL code.