Xilinx enables developers through the complete hardware design process with advanced design tools; real-time and post-run analysis and optimization for signal integrity, timing, RX margin, power, and foot print; physical and simulated-hardware support, and an extensive IP catalog.
Hardware Design Tools
Logic Design and Planning
Xilinx PlanAhead Design Tool supports RTL design in Verilog or VHDL with a focus on function, features, design efficiency, and analysis capabilities to the user.
- A comprehensive cockpit for creating and verifying RTL designs in either Verilog or VHDL
- Access to the Xilinx IP catalog through CORE Generator integration
- Quickly elaborate RTL sources to show schematic view, resource and power estimation
- Manage synthesis with Xilinx Synthesis Technology (XST)
- Perform behavioral and functional verification of HDL code and IP at various stages of the design with with ISE® Simulator
- Automatically or manually assign I/O ports to physical package pins
- Experiment with different HDL, tool options, and floorplanning trials to determine how the design is affected
- Execute multiple implementation scenarios based on user, or Xilinx-defined strategies
- Employ cross-probing for designs analysis and issue tracking
- Trace issues such as timing violations and DRCs back to schematics, netlists and constraints
- Experiment with physical constraints such as pblocks (area groups) and location constraints for cell instances
- Estimate, analyze and optimize power consumption from pre-design through to implementation with XPE (PDF)
- Choose board parts and design based on power estimates and system reliability requirements
- Statistical analysis of electrical signal integrity
- Analyze pinouts for Simultaneous Switching Noise (SSN) or Weighted Average Simultaneous Switching Output (WASSO), based on device family
- Limit the amount of ground bounce present immediately at the output of the FPGA and prevent corruption of the operation of other devices driven by the FPGA
- Estimate route delays before running place and route with the integrated timing analyzer
- Perform early path delay estimates to assist with floorplanning and detailed path tracing, debugging and constraint assignment
- Use the AXI Bus Functional Model to simulate custom-designed AXI-based IP
- Begin your custom design with example test benches and tests for AXI3, AXI4, AXI4-Lite and AXI4-Stream Master/Slave BFM pair
- Perform transaction level protocol checking (burst type, length, size, lock type, cache type)
Integrate Plug-and-Play 3rd Party IP
Xilinx offers a catalog of plug-and-play IP ready to be integrated with your design and tools that migrate algorithms and functions to RTL.
- Embedded processing peripheral IP cores
- Standard peripherals and devices to accompany a typical embedded processor design
- Standard processor devices and buses - MMU, pipeline, IO, buses
- MicroBlaze soft core microprocessor configurable from minimalist state-machine configurations up to a general purpose embedded processor
- Logic and Connectivity IP cores
- Architecture, domain (embedded, connectivity, and DSP), and market specific IP, ranging in complexity from commonly used functions, such as memories and FIFOs, to system-level building blocks, such as filters and transforms
- User-customizable
- Save days to months in hardware design
- Xilinx System Generator for DSP provides system modeling and automatic code generation from Simulink® and MATLAB® (The Mathworks, Inc.)
- Integrates RTL, embedded, IP, MATLAB and hardware components of a DSP system
- Xilinx Vivado High-Level Synthesis directly targets C, C++ and System C specifications into FPGAs without the need to manually create RTL
- Automatic use of Xilinx on-chip memories and DSP elements, Xilinx floating point library and IP components such as MPMC, PLB, and FSL
- Multi-language support and the broadest language coverage in the industry
- Fast time to QoR that rivals hand-coded RTL
Implement
Xilinx ISE Design Suite provides Xilinx-optimized map, synthesis, place and route and bitstream generation functions.
- Map, Place and Route - optimized for performance, power, footprint
- Auto-generated timing reports
- Manage alternative HDL, tool options and floorplanning trials with exploration tools in order to achieve design requirements
- Manage multiple runs, allowing you to execute multiple trials based on user-defined strategies or predefined factory strategies
- Synthesize HDL into netlists - Verilog and VHDL, optimize for Xilinx silicon, performance optimization, power optimization, visualize RTL Netlist with viewer
- Optimize physical synthesis through techniques such as register balancing, global optimization, timing-driven synthesis, and logic optimization
- Integrate 3rd party IP cores with in-house developed cores
- Synthesize with Synopsys Synplicity
Verify
Xilinx ISE Design Suite generate Timing, BER, and signal integrity analysis reports during the implement phase. This information combines with output from advanced simulators and debuggers, and advanced chip probes to verify the design at both RTL and silicon throughout the whole design process.
- Includes embedded soft processors
- Analyze in real-time or post-run
- Use advanced trigger and capture enhancements for repetitive measurements
- Add debug probes directly in HDL (VHDL and Verilog) or constraint files
- Change probe points without re-implementing the design
- Debug over a network connection using remote debug, from your office to the lab, or across the globe
- Choose from multiple RTL simulation options
- Aldec Riviera-PRO
- Mentor ModelSim
- Synopsys VCS
- Xilinx iSim
- Mixed language VHDL-93 and Verilog 2001
- Supports AXI Bus Functional Model (BFM)
- Multi-Threaded compilation
- Post-Processing capabilities
- Tcl scriptable GUI and batch mode simulation run
- Standalone Waveform viewing capabilities
- Debug capabilities
- Waveform tracing, waveform viewing, HDL source debugging
- Power Analysis and optimization using SAIF
- Memory Editor for viewing and debugging memory elements
- Easy to use - One-click compilation and simulation