Define and build custom Zynq™-7000 All Programmable SoC (AP SoC) designs with advanced graphical system configuration tools, the Xilinx IP catalog, high-level synthesis, and the Zynq-7000 AP SoC virtual platform.
System Design
Architecture Definition
Xilinx tools and IP libraries architecture definition tasks through plug-and-play IP cores, high-level functional models, and advanced algorithm to RTL solutions.
Integrate AXI IP cores from the Xilinx IP catalog of architecture specific, domain-specific (embedded, connectivity, and DSP), and market specific IP, ranging in complexity from commonly used functions, such as memories and FIFOs, to system-level building blocks, such as filters and transforms.
- Audio, Video and Image processing
- Automotive
- Basic Logic
- Bus interface and IO
- Communications and networking
- Digital Signal Processing
- Embedded Processing
- FPGA-specific features and debug
- Math
- Memory interface and storage
- Storage, NAS and SAN
- Vivado™ High-Level Synthesis allows developers to target C, C++ and System C specifications into FPGAs without the need to manually create RTL.
- Automatic use of Xilinx on-chip memories and DSP elements, Xilinx floating point library and IP components such as MPMC, PLB, and FSL
- Multi-language support and the broadest language coverage in the industry
- Fast time to QoR that rivals hand-coded RTL
The Zynq-7000 AP SoC Virtual Platform supports system design exploration and prototyping, software development and debug, software systems integration, and system test with metric driven hardware and software verification of Zynq-7000 AP SoC based designs.
- Transaction Level Models for Zynq-7000 AP SoC processor and processing system
- Extensible to model IP cores included within the programmable logic
- For architecture exploration and system design
Processor Configuration
Xilinx Platform Studio (XPS) makes it fast and easy to configure the Zynq-7000 AP SoC processing subsystem and peripherals, Xilinx support for AXI-based IP cores and our large library of AXI devices offers hundreds of customization possibilities.
- Xilinx XPS provides extensive GUI-driven capabilities for connectivity and parametric (e.g. clock or memory device) configuration of custom Zynq designs
- Configure clocks, memory buses, peripherals
- Guaranteed correct connection between processing system and programmable logic
- Voltage and Pin-aware
- Exports configuration for auto-generation of First Stage Boot-loader, Bare metal BSP and Linux BSP
- Xiinx and 3rd party embedded IP enables developers to customize their design with validated, ready-to-go IP cores.
- Create hundreds of custom Zynq AP SoC configurations with plug-and-play IP cores including:
- Microprocessor and microcontroller
- Interface / Bus / Bridge
- Communications and Infrastructure peripherals
- Graphics interfaces
- Hardware Debug Enhancements
- Create hundreds of custom Zynq AP SoC configurations with plug-and-play IP cores including: