Superior Clock Management

Clocking Flexibility Reduces Power Consumption

In today’s rapidly growing high technology electronic designs, clock management has become increasingly more important to achieve required performance and to reduce power consumption. CoolRunner™-II CPLDs address this challenge by providing superior clock management for improved performance and power management.

CoolCLOCK
DualEDGE Flip-Flop

Clock Divider
Clock Doubler

Learn more about CoolRunner-II Clock Management

Using CoolRunner-II Advanced Features (PDF)

CoolRunner-II Technology & Architecture Module (PDF)

CoolRunner-II DDR Memory Interface(PDF)

Clock Divider

Clock Divider improves power savings by providing clock division at standard values. CoolRunner-II CPLDs give the designer unsurpassed clock management features that enable an easy to implement total clock management solution.

Gives solid clock division without using macrocells
Duty cycle improvement
Available in large densities (128 macrocells and above)
Very low lag ...typically 50 ps!

Clock Divide

Figure 1

Clock Divider provides clock division at standard values (2 though 16).

Clock Doubler

The Clock Doubler enhances performance by doubling the internal clock speed. It is selectable for each macrocell and is ideal for Double Data Rate (DDR) memory devices.

Doubles internal clock speed up to 400 MHz
Available for each macrocell

CoolCLOCK

CoolCLOCK is a combination clock divider and clock doubler that divides the incoming clock by two and then doubles the clock at the output level to maintain the same performance while reducing the internal power consumption.

Combines clock divider and doubler
Divides incoming clock by 2
Reduces overall clocking power

DualEDGE Flip-Flops

Most programmable logic devices allow for the clocking of a macrocell on the rising edge of a clock or on the falling edge of the clock signal. CoolRunner-II CPLDs with the help of dualEDGE flip-flops, allow for clocking on both edges. This capability increases the effective synchronous operation rate of any design up to the bandwidth limits of the device. In other words, you can operate any sequential design twice as fast for a given clock rate, or do the same amount of processing for 1/2 the external clock frequency.

Distributes divided clock globally then double locally at macrocell
Use 2x clocking for double data rate applications
No additional insertion delay
Available in all CoolRunner-II CPLDs

DualEDGE Flip-Flops

Figure 2

DualEDGE flip-flops allow for clocking on both edges.