Xesium Clocking

Enhanced Clocking Helps You to Achieve Highest Performance

Virtex™-4 FPGAs incorporate advanced clocking capabilities that help you to achieve highest performance by minimizing clock jitter, skew, and duty cycle distortion. Xesium clocking makes it easy to place and route large designs, with abundant, fully flexible clock resources that eliminate constraints encountered in previous generation FPGAs. ChipSync™ technology makes it easy to build source-synchronous interfaces with built-in circuitry for aligning clock and data signals at physical interfaces, without using multiple digital clock managers (DCM) or local clocking resources.

Abundant clock resources

32 clock inputs (differential or single-ended)
32 global clock networks
16-48 regional clock networks
8-24 distinct clock regions

Abundant clock management features

Up to 20 Digital Clock Managers (DCMs)
Up to 8 Phase Matched Clock Dividers (PMCDs)
32 Global Clock Buffers

High Performance

500 MHz clocking throughout the chip
30% reduction in jitter
Automatic duty cycle precision

Easy design

Quadrant and buffer restrictions eliminated
Enhanced Clocking Wizard for design generation
New automatic jitter and skew reporting for timing budgets

Digital Clock Managers (DCM)

DCMs deliver sophisticated digital clock management resistant to system jitter, temperature, voltage variations and other problems typically found with PLLs integrated into FPGAs.

Clock deskew

Delay-locked loop (DLL) completely eliminates clock distribution delays

Phase shift control

Coarse (quadrature) phase shifting
Fixed and variable fine-grained phase (1/256 clock period) shifting modes for clock/data synchronization
Direct DCM phase-shift control for advanced applications

Flexible frequency generation from 24 MHz to 500 MHz

Integer multiplication and division parameters

Dynamic reconfiguration of DCM multiply, divide, and phase shift

Two performance modes

Maximum Speed - maximum frequency, minimum jitter
Maximum Range - minimum frequency, widest phase shift range, lowest power

Phase-Matched Clock Dividers (PMCD)

A Virtex-4 clock management enhancement, PMCDs provide improved handling of multiple synchronous clock domains.

Phase-matched divided clocks

Create up to four frequency-divided and phase-matched versions of an input clock
Divide by 1, 2, 4 or 8
Divided clocks are rising-edge aligned

Phase-matched delayed clocks

Preserve edge alignments and phase relations between the divided clocks and other clocks

Global Clock Buffers

Fully differential buffering and routing
Fully flexible programming
Use as a buffer or a mux
Use for synchronous or asynchronous switching
Optional tri-state enables
Optional clock enables

Virtex-4 Clock Management Resources
Clock pins: differential or single-ended	32
Clock regions	8-24 regions
Global clocks	32 total, 8 per region
Regional clocks	16-48 total, 2 per region
Total dedicated clocks	48-80
I/O banks	9-17 full-featured
Clock circuits	20 DCMs + 8 PMCDs
Maximum clock speed	500 MHz
Frequency synthesis	M, D: 1..32
Phase shifting	20 ps precision