Signal Integrity

Solve Signal Integrity Challenges

Controlling crosstalk improves system performance for wide single-ended I/O interfaces such as DDR2, DDR, RLDRAM-II, and QDR II memory interfaces. Virtex™-5 FPGAs help simplify board design, reduce design cycles, lower system cost when designing wide memory and high-speed interfaces by:

• Minimizing inductive crosstalk
• Reducing the number of external decoupling capacitors
• Lowering inductance
• Reducing board layer count

The dense via field under a BGA package fills with inductive noise as hundreds of I/O pins switch. Lab measurements and simulations conducted by renowned signal integrity expert Dr. Howard Johnson show that the advanced sparse chevron packaging technology Xilinx first introduced with Virtex-4 FPGAs provides significant, measurable reduction in SSO noise/crosstalk compared to traditional FPGA package design.

Optimal Solution for Power Distribution System Design

Virtex-5 sparse chevron packaging effectively positions bypass capacitors on-substrate, next to the FPGA die I/O. Thus, you can reduce BOM costs and shrink PCB area by removing hundreds of discrete capacitors from the PCB. The enhanced pin layout created for Virtex-5 FPGAs also simplifies I/O routing breakout to further reduce PCB layer count and design costs.