ExpressFabric Architecture

Two speed-grade performance increase, 35% lower dynamic power, 45% less area

Using revolutionary ExpressFabric™ architecture, the Virtex™-5 FPGAs deliver significant improvements over previous generation FPGAs.

In depth

Delivering the industry's first Real 6-input Look-up Tables (LUT), ExpressFabric technology allows you to configure LUTs as either 6-input or dual-output 5-input generators. You can now implement larger functions such as 256 bits of distributed RAM, 128-bit long shift registers and 8-input functions within a single Configurable Logic Block (CLB). The following graphic shows how you can fit wider functions and distributed memory into fewer LUTs:

Figure 1

Example: Implementing 64-bit Distributed RAM

The Virtex-5 family uses diagonally symmetric interconnects to minimize routing hops - the number of interconnects required from CLB to CLB - to realize major performance improvements.

Figure 2

Previous interconnect technology and Virtex-5 FPGA leadership

Table 1: Virtex-5 and Virtex-4 FPGA Architecture Features
Features	Virtex-5	Virtex-4
Logic cells*	330,000	200,000
Logic fabric	Real 6-input LUT	4-input LUT
Distributed RAM	256 bits per CLB	64 bits per CLB
Shift registers (SRL)	32-bit (or 2x 16-bit)	16-bit
Interconnect	Diagonally symmetric routing	Segmented routing
CLB architecture	Two slices, each comprising four Real 6-input LUTs and four Flip-Flops	Four slices, each comprising two 4-input LUTs and two Flip-Flops
Manufacturing technology	65nm triple-oxide	90nm triple-oxide

* Industry defines a logic cell as a 4-input Look-up Table and a Flip-Flop.