| 550 MHz Performance |
Extract maximum through-put from logic fabric and hard IP |
Up to 6 Clock Management Tiles (CMT)
- Up to 12 DCMs
- Up to 6 PLLs
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Provide a flexible high performance clock management solution |
| Clock Deskew |
Provide zero propagation delay between source clock and output clock, low clock skew among output clock signals, and advanced clock domain control |
| Frequency Synthesis |
Easily multiply or divide clock frequencies, or create custom-synthesized M/D frequencies |
| Phase Shifting |
Achieve your exact phase requirements with coarse and fine-grain phase shifting |
| Dynamic Reconfiguration |
Change DCM attributes without reconfiguring the rest of the device |
Flexible DCM-to-PLL or PLL-to-DCM cascade |
Optimize low-jitter clock generation |
| Jitter Filtering |
Reduce clock jitter by 50% or more |
Abundant Clock Resources
- 20 clock inputs (differential or single-ended)
- 32 matched-skew global clock networks
- 4 I/O clock nets and 4 Regional clock nets per clock region
- 8-24 distinct clock regions
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Ensure clock alignment and overall system level timing for large designs. Include and manage multiple time domains in a single device. Simplify source-synchronous interfaces with I/O clocks and regional clocks |
