Device Configuration

      

Enhanced Configuration and Bitstream Protection

Virtex®-5 FPGA configuration options help you reduce system cost, increase reliability, and safeguard your design.

Low-cost configuration options

• SPI flash memory
• Parallel flash memory
• Xilinx configuration memory devices

Enhanced Bitstream Management

Simplify in-system reconfiguration and increase reliability with:

• Multi-Bitstream Management Support supports warm/cold boot of the FPGA as well as providing for a safe bitstream if FPGA errors occur.
• Background CRC checking capability is implemented.

Figure 1

Virtex-5 Device Configuration

AES Bitstream Encryption/Decryption Technology

Protect your intellectual property with security you can bank on. Virtex-5 FPGAs protect your design with AES (Advanced Encryption Standard) technology.

• Software-based bitstream encryption and on-chip bitstream decryption logic uses dedicated memory to store the 256-bit encryption key.
• You generate the encryption key and encrypted bitstream using Xilinx ISE® software. During configuration, the Virtex-5 device decrypts the incoming bitstream.

Battery-backed Key Provides Unbreakable Security

Xilinx security makes it virtually impossible for thieves to steal your design data. The encryption key is stored internally in dedicated RAM. Backup is effected by a small, externally-connected battery (typical life 20+ years).

• The encryption key cannot be read out of the device.
• Unlike non-volatile key storage methods, any attempt to remove the Virtex-5 FPGA and decapsulate the package for probing results in the instant loss of the encryption key and programming data.