Competitive Advantage through Productivity

Giving Xilinx XtremeDSP Customers the Competitive Edge
The Xilinx XtremeDSP™ design flow, using the System Generator for DSP software platform, provides multiple benefits for the whole DSP design team by accelerating overall team productivity, and thereby helping our customers to get to market much faster. Through the use of the tool and Xilinx DSP training classes, designers can improve their overall design capabilities and knowledge base. All these elements contribute in helping Xilinx customers develop a significant competitive edge for doing high-performance DSP designs.

Benefits for System Architects/DSP Designers

System Architects/DSP designers are typically involved in developing system models, doing concept testing and typically tend to use high-level languages such as C, C++, MATLAB®, and tools such as Simulink® for development. These engineers often do not have intimate knowledge of VHDL and FPGA development. The key benefits for these designers in using Xilinx XtremeDSP design flow include the following:

• The ability to concentrate on their area of expertise as detailed knowledge of FPGA architectures not required
• The ability to make early cost/performance trade-offs on precision and speed through doing bit- and cycle-true simulations at the front-end using Simulink.
• Fast time-to-market
• The ability to leverage extisting tools like MATLAB/Simulink and use System Generator for DSP as an "on-ramp" to developing TeraMACs/s DSP designs using the industry's leading Virtex-II series FPGAs
• The ability to take HDL code from the FPGA designer and import it into the system-level simulation
• The ability to verify and accelerate designs in hardware using hardware in the loop

Benefits for Digital/FPGA Designers

Digital/FPGA Designers are typically involved in developing, verifying and implementing hardware using languages like VHDL and Verilog HDL, and EDA tools for simulation, place androuting designs. Often these designers do not have intimate knowledge of high level languages such as MATLAB or C++. The System Generator for DSP therefore provides Digital/FPGA designers with the following benefits:

• The ability to shorten design iterations through receiving an executable spec hand-off from the system designers
• Receiving bit- and cycle-true models from Simulink means fewer design iterations
• The ability to automatically generate test-bench and vectors using Simulink
• Gaining easy access to the industry's most advanced high-performance DSP IP libraries/algorithms from Xilinx
• The ability to automatically generate documentation for the design
• Access to silicon features to optimize performance and area
• The ability to verify and accelerate designs in hardware on preferred hardware using hardware in the loop