-Dallas Pace, Section Manager, Digital Hardware Engineering for DRT, Inc.
Optimized for DSP applications for highest system integration, Spartan®-3A DSP FPGAs are ideal for cost sensitive DSP algorithmic and co-processing applications requiring significant DSP performance.
Dual power management modes allow the device to go to an extremely low power state which can reduce power consumption significantly.

* Available only in largest two devices.
Four level memory architecture

Extended Spartan-3A FPGAs support multiple platform standards

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Spartan-3A DSP FPGA Family: Complete Data Sheet
This data sheet provides a summary of the Spartan-3A DSP FPGA family features and specifications.
XtremeDSP DSP48A for Spartan-3A DSP FPGAs User Guide
This user guide is a detailed functional description of XtremeDSP™ Solution Spartan-3A DSP technology.
Spartan-3 Generation FPGA User Guide
Functional description of the Spartan-3 Generation family architecture and how to use it. Includes the Spartan-3A, Spartan-3AN, Spartan-3A DSP, Spartan-3E, and Spartan-3 platforms.
All Spartan-3A DSP FPGA Documentation
Access all the available documentation for Spartan-3A DSP FPGAs.
XtremeDSP Starter Platform – Spartan-3A DSP FPGA 1800A Edition
This evaluation platform delivers instant access to Spartan-3A DSP family capabilities and supports industry-standard peripherals, connectors, and interfaces.
XtremeDSP Video Starter Kit — Spartan-3A DSP FPGA Edition
The XtremeDSP™ Video Starter Kit – Spartan®-3A DSP FPGA Edition is the ideal hardware platform to evaluate Xilinx FPGA(s) in a wide range of Video and Imaging applications.
XtremeDSP Starter Kit - Spartan-3A DSP FPGA 1800A Edition
This evaluation platform delivers instant access to Spartan-3A DSP family capabilities and supports industry-standard peripherals, connectors, and interfaces.
All Spartan-3A DSP FPGA Boards
Access all the available boards and kits for Spartan-3A DSP FPGAs.
CoreConnect™ is an IBM-developed on-chip bus-communications link that enables chip cores from multiple sources to be interconnected to create entire new chips.
XPS_LL_TEMAC Ethernet core provides a control interface to internal registers via a 32-bit Processor Local Bus (PLB) Version 4.6 as described in the IBM CoreConnect™ 128-Bit Processor Local Bus, Architectural Specification Version 4.6.
The FIR Compiler v4.0 reduces filter implementation time to the push of a button, while also providing users with the ability to make trade-offs between differing hardware architectures of their FIR Filter specification.
Access all the available IP for Spartan-3A DSP FPGAs.
Lowest Total Cost with Spartan-3 Generation FPGA
In today's world consumer prices are projected to continue to decline, and now more than ever you need a low cost solution.
Designing Embedded Systems With Linux and Low Cost FPGAs
Learn about the increasing challenges of designing connected embedded systems and how to solve some of them with flexible hardware and software platforms.
Featuring Low Power FPGA and Analog Solutions with Spartan-3 Generation FPGA
Learn about on-chip power management modes, power-saving techniques, and power management solution options in Spartan-3 generation FPGAs.
All Spartan-3A DSP FPGA Videos
Access all the available videos for Spartan-3A DSP FPGAs.
This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs.
Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® 9.1i tool suite and Xilinx hardware.
Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.
Access all the available training for Spartan-3A FPGAs.
From documentation to tools and IP, Xilinx has the support you need for Spartan-3A DSP FPGA devices.
Configuration Memory for Spartan FPGA
Maximize the flexibility of your system and reduce the amount of board space required for your configuration.
Access the promotional documentation available for Spartan-3A DSP FPGAs.