Connectivity

• Virtex-6 HXT FPGA with up to 72 serial I/O channels (24 GTH transceivers and 48 GTX transceivers) provide over 0.5Tb/s serial I/O bandwidth to design 40G and 100G applications in a single FPGA
  • When combined, the select IO bandwidth the aggregate IO bandwidth is over 1Tbps
• Virtex-6 LXT and SXT FPGAs deliver GTX transceivers
  • Most flexible transceiver in any FPGA
  • Enables designing with a multitude of serial protocols
  • Industry’s best hardware PCS features that simplify usage
  • Aids faster debug and accelerates adoption of complex serial protocols for all applications
• Spartan-6 LXT FPGAs are the lowest cost FPGAs with GTP serial transceivers
  • Optimized to fully support the most common serial standards: PCI Express®, Gigabit Ethernet, Display Port and more
  • Highly efficient and dedicated clocking sources enables each GTP transceiver to be configured to support a different serial protocol
• All Xilinx Virtex-6 and Spartan-6 FPGAs also include configurable SelectIO™ technology to support multi-voltage, multi-standard parallel connectivity technologies – HSTL, LVDS (SDR and DDR) and more

The ISE Design Suite: Logic Edition delivers a complete solution for connectivity design providing the front-to-back methodology and IP required to enable designers to achieve greater designer productivity, focus on design differentiation, shrink time to production, attain breakthrough performance, power and cost benefits.

The Logic Edition includes Xilinx exclusive tools and technologies for design entry, synthesis, implementation, and verification to help achieve optimal design results in the shortest time.

Complete high-speed serial design methodology and tool flow

• Design Tools: ISE Design Suite Logic Edition
  • Architecture Wizards – Transceiver, Clocking, CRC Wizards
  • Design analysis and synthesis – PlanAhead™ (FloorPlanning and PinLayout), XST
  • Implementation tools – MAP, Timing driven P&R, SmartXplorer
  • Debug tools – ChipScope™ Pro, SerialIO ToolKit, FPGA Editor, IBERT LogiCORE™
• Guidelines and reports
  • Signal integrity considerations
  • Transceiver characterization general and protocol specific reports
• Documentation
  • Datasheets and user guides
  • White papers
  • Application notes
  • Reference designs

Xilinx provides end-to-end connectivity solutions supporting serial and parallel protocols. The support for many of these protocols is provided through Xilinx IP LogiCOREs that enable you to maximize design flexibility and reduce risk. In addition they are pre-verified for serial I/O standards and are certified through industry-wide IP interoperability and certification programs. All Xilinx IP is delivered through the CORE Generator™ system to help streamline your design process and improve design quality.

Xilinx support for protocols and technology

Learn more about how support for the AXI4 Interface Protocol offers greater productivity, flexibility, and availability for FPGA designers.

Certification

• Xilinx provides a UNH tested Ethernet IP cores with integrated serial interface to ensure first time success
• SPI-4.2 core interoperability testing completed with leading framers (e.g. PMC, Vitesse) and NPUs (e.g. Netronome IXP2800)
• Passes all PCI-SIG specified compliance tests for PCI Express and listed on PCI-SIG integrators list

Additional IP is available through the Xilinx IP Center.

Xilinx provides a complete connectivity design environment through evaluation kits to accelerate design development by integrating critical components required for creating an application targeted towards Xilinx FPGAs.

Development kits to prototype, evaluate and debug your FPGA design implementations

• Development Kits
  • Virtex-6 LXT FPGA Connectivity Kit
  • Spartan-6 LXT FPGA Connectivity Kit
• Evaluation kits
  • Virtex-6 FPGA ML605 Evaluation Kit
  • Spartan-6 FPGA SP605 Evaluation Kit
• All Xilinx Virtex-6 and Spartan-6 FPGA boards include a FPGA Mezzanine Card (FMC) connector on the board
• FMC daughter cards

Targeted reference designs to accelerate your design development

• Delivered with connectivity kits
• Design framework
  • Demonstrates critical components working together in a system environment
• Maintained/ updated with ISE Design Suite release
• Fully supported
• Integrates Xilinx and other 3rd party IP deliverables
• Extends functionality of the evaluation kits through design and/ or hardware