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56G PAM4 Technology

Enabling Next Wave of Ethernet Deployment

Industry Leading Transceiver Technology

To help drive the next wave of Ethernet deployment, Xilinx has developed a FinFET+-based programmable device running 56Gb/s transceivers. The new architecture:

  • Breaks through the physical limitations of data transmission at 50G+ line rates
  • Features next generation equalization technologies to minimize channel loss
  • Supports chip-to-chip, module, direct-attach cable, and backplane communication

PAM4 Modulation as the Way Forward

PAM4 (or 4-level Pulse Amplitude Modulation) has been recognized as the most scalable multi-level signaling protocol for next-generation line rates, and Xilinx is helping drive 56G PAM4 standardization efforts within both the Optical Internetworking Forum (OIF) and the Institute of Electrical and Electronics Engineers (IEEE).

Paving the Way Forward for Next Generation Ethernet

Cloud Computing, Industrial IoT, and Software-Defined Networks applications, to name a few, continue to accelerate and drive the need for unlimited bandwidth. The latest transceiver architecture will enable vendors to

  • Double bandwidth on existing infrastructure
  • Scale 50G, 100G, 400G ports, as well as terabit interfaces
  • Evaluate the technology to develop their own next generation solutions

Next generation, standardized line rates are critical to meeting these ongoing bandwidth requirements.

Developer Zone

For FPGA designers looking to shorten design time and ensure scalability and re-use, Xilinx provides a comprehensive suite of solutions ranging from C-based design abstractions to IP plug-and-play to address bottlenecks in hardware development, system-level integration, and implementation.