To help drive the next wave of Ethernet deployment, Xilinx is integrating 56Gb/s transceivers into its 16nm FinFET+ Virtex® UltraScale+™ FPGA family. The new transceiver architecture:
PAM4 (or 4-level Pulse Amplitude Modulation) has been recognized as the most scalable multi-level signaling protocol for next-generation line rates, and Xilinx is helping drive 56G PAM4 standardization efforts within both the Optical Internetworking Forum (OIF) and the Institute of Electrical and Electronics Engineers (IEEE).
Cloud Computing, Industrial IoT, and Software-Defined Networks applications, to name a few, continue to accelerate and drive the need for unlimited bandwidth. The latest transceiver architecture will enable vendors to
Next generation, standardized line rates are critical to meeting these ongoing bandwidth requirements.
For FPGA designers looking to shorten design time and ensure scalability and re-use, Xilinx provides a comprehensive suite of solutions ranging from C-based design abstractions to IP plug-and-play to address bottlenecks in hardware development, system-level integration, and implementation.