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Power Efficiency

Through silicon process selection, architectural innovation, and robust power estimation and optimization tools, Xilinx All Programmable devices continue to deliver unrivaled system-level power reduction with each successive generation of All Programmable logic families.

UltraScale Architecture Low Power Leadership for Next-Generation Systems

With UltraScale device families, a low-power semiconductor process coupled with significant static and dynamic power gating results in up to 45% overall device-level power savings at 20nm over Xilinx 7 series FPGAs and SoCs —already the lowest-power programmable logic device leader. In addition to process node benefits at 20nm and 16nm, designers can leverage key architectural enhancements such as hardware-based clock gating, hardened BRAM cascading, DSP block efficiencies, and optimized transceivers to lower overall power consumption.

Through device-level optimizations and systems integration, UltraScale devices deliver dramatic system-level power savings over previous implementations:

Industry Application
System-level Power Savings
Wired Communications
400G MAC to Interlaken Bridge
60%
Data Center 100G NIC Packet Processing 50%
Wireless Communications DFE 8x8 100MHz TD-LTE Radio 30%
Medical 256-Channel UltraSound 50%
Test & Measurement ASIC Prototyping 35%

7 Series FPGAs Power Innovation and Execution

As the only 28nm FPGAs and SoCs fabricated on a high-performance, low-power process (28HPL), 7 series devices offer lower total power consumption and superior performance per watt compared to competing solutions. Architectural and block level innovations unique to Xilinx add to the power advantages at every level. In addition, to ensure a smooth production rollout of your system, 7 series FPGAs and SoCs provide:

  • Credible power estimation and optimization
  • Stable power specifications
  • Available device power options

View the latest 7 series power benchmarks.

Credible Power Estimation and Optimization

Meeting system power, thermal, and reliability requirements starts with credible power estimation and optimization.

Xilinx Power Estimator (XPE)

The Xilinx Power Estimator (XPE) provides accurate power estimation, helping designers avoid costly power supply and thermal management changes late in the design cycle. XPE is transparent about all sources of power consumption to ensure a complete picture of the total power budget.

Competing solutions claim “lower power” by not discussing some sources of power consumption. For instance, competitors promote transceiver power based only on the PMA power. Transceiver power is actually the sum of the PMA, PCS, and static power associated with transceiver usage.

Transceiver Power (4 Channel Design) – Lower is Better

transceiver-power

Vivado Power Analysis

The Vivado™ Design Suite offers powerful and accurate power analysis, including:

  • Graphical and textual views of power consumption by design hierarchy, block type or by voltage rail.
  • Advanced cross-probing capabilities from the power report to HDL, schematics or the FPGA device view.
  • Ability to accept switching activity information from VCD, and SAIF files for more accurate power estimation.
  • Support for “what if” scenarios to further reduce power.

Vivado Power Optimization

Vivado offers push button power optimization that reduces dynamic power by an average of 18% and up to 30% with virtually no impact to performance.  Fine-grained clock gating technology is automatically applied to reduce switching activity.  Other FPGA companies claim to offer similar power optimization, but analysis of these solutions shows either minimal power reduction (default mode) or a major impact to performance (full power optimization mode).

Design Tool Power Optimization Analysis (Average of 30 designs)

POWER OPTIMIZATION XILINX COMPETITOR
Default Power Optimization Reported Dynamic Power Savings 7.5% 2%
Performance Change 0% -1%
Full Power
Optimization
Reported Dynamic Power Savings 18% 12%
Performance Change -1% -9%

Stable Power Specifications

Every 7 series device is tested to published max static power specs to ensure power consumption at or typically below expectations.  Competing solutions have repeatedly raised static power specs near or after production, or simply failed to report maximum static power altogether, forcing designers to re-evaluate system demands.

Max static power changes near or after entering production

28nm FAMILY XILINX COMPETITOR
Low end No Change No Max Static Power
Mid Range No Change ~ 50% Increase
High End No Change ~ 10-30% Increase

Available Device Power Options

Xilinx 7 series FPGAs and SoCs support power binning of devices to provide lower static and total power. Well-defined yield and process distribution models ensure a reliable supply in volume production.  Competitors have introduced power binned devices only after standard devices failed to meet the original static power specifications in production, leaving questions around the volume availability of these products.

Comparison of reduced static power device options

28nm FAMILY XILINX COMPETITOR
Device Offering -1I/-2I -1I/-2I -2LE(0.9V) -1LI/-2LI "L" Devices
Static Power Reduction 30% 45% 55% 62% - 65% 30%
Planned From Beginning After Production
Availability Volume Production After Production

7 Series Power Benchmark Examples

The following total power benchmarks represent real application designs, demonstrating the power-efficiency leadership of Xilinx 7 series devices.

Artix®-7 FPGA Application Power Benchmarks

Kintex®-7 FPGA Application Power Benchmarks

Virtex®-7 FPGA Application Power Benchmarks

Zynq®-7000 Application Power Benchmarks

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