Product|devices

Virtex-5 FPGA Family

Virtex-5 TXT Webcast

Virtex®-5 FPGAs are the world’s first 65nm FPGA family fabricated in 1.0v, triple-oxide process technology, providing up to 330,000 logic cells, 1,200 I/O pins, 48 low power transceivers, and built-in PowerPC® 440, PCIe® endpoint and Ethernet MAC blocks, depending upon the device selected.

Virtex-5 Benefits
Breakthrough price / performance value with built-in functionality
  • Two speed-grade performance gain with ExpressFabric™ technology
  • 550 MHz high precision, low jitter clocking with clock management tile
  • 150 Mbps - 6.5 Gbps high performance serial connectivity with RocketIO™ GTX transceivers
  • Performance-tuned IP blocks
  • 1100 DMIPS per PowerPC 440 processor block with high-bandwidth, low-latency interfaces
  • 528 GMACs from 550 MHz DSP48E slices with 25x18 multipliers for DSP acceleration
  • 192 GFLOPS single-precision and 68 GFLOPS double-precision floating point DSP
  • Simplified source-synchronous interfacing with 1.25 Gbps LVDS I/O and ChipSync™ technology
  • 550 MHz, 36Kbit Block RAM/FIFO with built-in error check and correction (ECC)
  • Enhanced configuration circuitry to support commodity flash memories, simplify system reconfiguration, and provide fifth-generation design security to protect your IP
  • System Performance Comparison
    Table 1

    System Performance Comparison

Power optimization strategies
  • 100 Mbps - 3.75 Gbps low power serial connectivity with RocketIO GTP transceivers: less than 100 mW (typ.) at 3.2 Gbps
  • 35% lower dynamic power delivered by 65nm ExpressFabric technology and power-saving IP blocks
  • Triple-oxide technology maintains static power at 65nm equivalent to 90nm Virtex-4 FPGAs. Hardened PCI Express® compliant endpoint blocks and Tri-mode Ethernet MACs
  • Advanced equalization to drive backplanes beyond 40”
  • Protocol kits accelerate development
  • Triple-oxide technology for reduced static power
    Figure 1

    Triple-oxide technology for reduced static power.

  • Power consumption and area required to implement a typical design including 8-lane PCIe endpoint.
    Figure 2

    Power consumption and area required to implement a typical design including 8-lane PCIe endpoint.

  • Power Savings Case Study : x8 PCI Express
    Table 1

    Power Savings Case Study : x8 PCI Express

Lowest system cost
  • Smaller device: 65nm process shrinks die size while new Real 6-input LUT increases efficiency
  • Fewer parts required when taking advantage of built-in low-power transceivers
  • Embedded processing systems can be integrated with PowerPC 440 block
  • Increased logic efficiency with built-in PCIe endpoint and Ethernet MAC blocks
  • Smaller heat sinks, fans, and power supplies enabled by reduced power consumption
Virtex-5 FPGA Sub-families
Virtex-5 LX FPGAs

For high performance logic

Virtex-5 LXT FPGAs

For high-performance logic with low power serial connectivity

Virtex-5 SXT FPGAs

For DSP and memory-intensive applications with low-power serial connectivity

Virtex-5 FXT FPGAs

For embedded processing with highest-speed serial connectivity

Virtex-5 TXT FPGAs

For ultra high-bandwith applications, such as bridging, switching, and aggregation in wired telecommunications and data communications systems

Virtex-5 FPGA Comparison Table
System Requirements LX LXT SXT FXT TXT
Logic        
High-density ASIC prototyping logic    
General purpose processing  
High-performance processing        
Digital signal processing      
Low-power serial I/O      
High-performance serial I/O      
System-on-chip design