ExpressFabric architecture for efficient, high-performance logic

Delivering the industry's first Real 6-input Look-up Tables (LUT), ExpressFabric technology allows you to configure LUTs as either 6-input or dual-output 5-input generators. You can now implement larger functions such as 256 bits of distributed RAM, 128-bit long shift registers and 8-input functions within a single Configurable Logic Block (CLB). The Virtex-5 family uses diagonally symmetric interconnects to minimize routing hops - the number of interconnects required from CLB to CLB - to realize major performance improvements.

Figure 1

ExpressFabric architecture

Figure 2

Implementing 64-bit Distributed RAM

Figure 3

Interconnect Technology

Table 1

Virtex-5 and Virtex-4  FPGA Architecture Features

550 MHz clocking for flexible, precise system clock management

Each clock management tile (CMT) uses two digital clock manager (DCM) blocks for precise clock synthesis and delay control, and one phase-locked loop (PLL) for low-jitter clock generation and jitter filtering. Up to six CMTs may be used for functions such as clock deskew, frequency synthesis, phase shifting, DCM>PLL or PLL>DCM cascade, and jitter filtering.

• 20 clock inputs (differential or single-ended)
• 32 matched-skew global clock networks
• 4 I/O clock nets and 4 Regional clock nets per clock region
• 8-24 distinct clock regions

Figure 1

Clock management

550 MHz block RAM for high-density embedded memory

5Up to 11.6 Mbits of flexible embedded Block RAM efficiently store and buffer data without off-chip memory. Each memory block stores up to 36 Kbits of data and can be configured as either two independent 18 Kb Block RAM, or 36 Kb Block RAM. Block RAM can be configured as dual-port RAM or as FIFO and offers 64-bit error checking and correct (ECC) to improve system reliability.

• Cascade Block RAM for true dual-port widths up to x36 or simple dual-port widths up to x72
• Create synchronous or multi-rate FIFOs using built-in FIFO logic; avoid consuming logic resources
• Turn off unused 18 kB Block RAM for enhanced power management
• Eliminate routing delay to CLB flip-flops for pipelined operation using optional output

Figure 1

Block RAM

1.25 Gbps SelectIO technology for ultimate parallel connectivity

Meet timing goals and reduce system costs with:

• High speed 1.25 Gbps differential and 800 Mbps single-ended I/O
• True 1.2V to 3.3V input voltage
• Pin-compatibility across entire family
• Up to 1200 I/O pins per FPGA and flexibility in I/O placement
• Source-synchronous ChipSync™ technology to simplify board design with built-in per-bit deskew, SERDES, adjustable tap delays, and input and output (Virtex-5 family only) delay components.
• Digitally-Controlled Impedance (DCI) with on-chip active I/O termination

Supported I/O standards:

• Virtex-5 FPGAs
  • LVCMOS 1.2V
  • HSTL_I_12 (unidirectional only)
  • DIFF_HSTL_I_18, DIFF_HSTL_I_18_DCI
  • DIFF_HSTL_I, DIFF_HSTL_I_DCI
  • DIFF_SSTL_I
  • DIFF_SSTL2_I_DCI
  • DIFF_SSTL18_I, DIFF_SSTL18_I_DCI
  • RSDS_25 (point-to-point)
• Virtex-5 and Virtex-4 FPGAs
  • LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
  • LVDS, Bus LVDS, Extended LVDS
  • SSTL (2.5v, 1.8v, Classes I, II)
  • LVPECL PCI™, PCI-X™ HyperTransport™ (LDT)
  • HSTL (1.8v, 1.5v, Classes I, II, III, IV)
  • GTL, GTL+

Figure 1

Enhanced SelectIO Technology

RocketIO GTP transceivers for lowest power

This fourth-generation RocketIO GTP transceiver technology delivers flexible SERDES with 100 Mbps-to-3.75 Gbps operating range that supports all popular protocols.

• Cross platform pin compatibility eases design upgrades to GTX transceivers for higher line rates
• Lowest power consumption in the industry: less than 100 mW per channel at 3.2 Gbps
• Multiple protocols (standard and custom) can be implemented in a single FPGA.
• Compliance with popular standards and protocols for chip to chip, backplanes and optical device interfaces
• Advanced Tx / Rx equalization techniques to drive backplanes and other difficult channels
• Built-in PRBS generator/checker accelerates debug
• Works seamlessly with integrated PCI Express® endpoint and tri-mode Ethernet MAC blocks

Figure 1

Standards support

RocketIO GTX transceivers for highest line rates

High performance SERDES with 150 Mbps - 6.5 Gbps operating range that supports all popular protocols. Cross-platform pin compatibility simplifies design upgrades from GTP transceivers for higher line rates.

• Multiple protocols (standard and custom) can be implemented in a single FPGA
• Advanced 4-tap Decision Feedback Equalization (DFE) combined with linear equalization in receiver to address signal integrity challenges at high line rates
• Transmitter pre-emphasis to improve signal integrity
• Integrated "gear box" for flexible encoding
• 8b/10b, 64b/66b, and 64b/67b
• Works seamlessly with integrated PCI Express® endpoint and tri-mode Ethernet MAC blocks
• Low power consumption:less than 200 mW at 6.5 Gbps
• Built-in PRBS generator/checker accelerates debug

PCI Express endpoint block for ubiquitous connectivity standard support

The PCI Express endpoint block implements transaction layer, data link layer, and physical layer functions to provide complete PCI Express endpoint functionality with minimal FPGA logic utilization.

• Conforms to PCI Express Base Specification 1.1
• Included on PCI-SIG® integrators list
• Supports PCI Express endpoint or legacy PCI Express endpoint functions
• Designed to provide complete endpoint functionality in conjunction with RocketIO™ transceivers
• 1-, 4-, or 8-lane support per block
• Uses Block RAMs for buffering
• Fully buffered transmit and receive
• Management interface to access PCIe Configuration Space and internal configuration
• Full range of maximum payload size (128 to 4096 bytes) supported
• Round robin, weighted round robin, or strict priority VC arbitration
• Base Address Registers(BARs) configurable for memory or I/O
• Up to 6 x 32-bit or 3 x 64-bit BARs (or a combination of 32 bit and 64 bit)
• Statistics collection and monitoring by signaling fabric
  
  Compliance Tested at PCI-SIG Workshops

The Xilinx Endpoint block for PCI Expressis on the PCI-SIG Integrators List, having successfully completed the following rigorous testing procedures of the PCI-SIG Compliance Workshop.

• FPGA Device
• Virtex-5 LXT, Endpoint Controller, PCIe 1.0a and 1.1
• Virtex-5 SXT, Endpoint Controller, PCIe 1.1
• Virtex-5 FXT, Endpoint Controller, PCIe 1.1
• Reference Board
• Virtex-5 LXT FPGA/ML505, PCIe 1.0a and 1.1
• Virtex-5 LXT FPGA/ML523, x1, PCIe 1.0a and 1.1
• Virtex-5 LXT FPGA/ML525, x1, PCIe 1.1
• Virtex-5 LXT FPGA/ML555, x4x8,PCIe 1.0a and 1.1
• Virtex-5 SXT FPGA/ML506, x1,PCIe 1.0a and 1.1
• Virtex-5 FXT FPGA/ML507, x1,PCIe 1.1

Figure 1

PCIe design example

Integrated tri-mode Ethernet Media Access Controller (EMAC) for internet connection

Two to eight embedded tri-mode Ethernet media access controller (MAC) blocks are available. 10/100/1000 Mbps tri-mode E MAC capabilities are IEEE 802.3 compliant and UNH-interoperability tested and certified. They offer:

• Programmable PHY Interface
• MII/GMII with SelectIO interface
• SGMII when used with RocketIO transceivers (requires external phy)
• Real-time statistics interface ports for performance monitoring of both Tx and Rx frames
• Jumbo frames support
• Receive address filter to accept/reject packets
• DCR-bus connection to microprocessors
• Complete single-chip solution for 1000 Base-X when using RocketIO transceivers (no external phy required)
• Ideal for network management or remote FPGA monitoring
• User configurable interface

Figure 1

Tri-mode Ethernet MAC

550 Mhz DSP48E slice for ultra-high performance DSP

Efficiently add powerful FPGA-based DSP functionality to your system with:

• 25-bit by 18-bit, two's complement multiplier with full precision 48-bit result
• Enhanced second stage that implements pattern detector for convergent rounding, underflow/overflow detection for saturation arithmetic, and auto-resetting counters/accumulators, and supports SIMD operations; also enable three input, flexible 48-bit adder/subtracter with optional registered accumulation feedback
• Support for over 40 dynamically controlled operating modes to adapt DSPE slice functions from clock cycle to clock cycle: includes multiplier, multiplier-accumulator, multiplier-adder/subtractor, three input adder, barrel shifter, wide bus multiplexers, wide counters, and comparators.
• Efficient adder-chain architectures for implementing high-performance filters and complex math efficiently.
• Low power requirements: each DSP48E slice draws only 1.38 mW/100 MHz, at a toggle rate of 38%, a 40% reduction from previous-generation slices.

Figure 1

DSP48E slice

High-performance PowerPC 440 processor block for area-efficient embedded systems

Up to two industry-standard PowerPC 440 processors with 32-bit RISC cores, each in its own embedded peripheral block.

• 1,100 DMIPS @ 550MHz processor; achieve 2,200 DMIPS using a single FPGA with two processors
• New 5 x 2, 128-bit crossbar switch minimizes latency and enables point-to-point connectivity
• Simultaneous memory bus and Processor Local Bus (PLB) access maximizes throughput
• Integrated DMA channels, PLB interfaces, and dedicated memory interface minimize logic utilization
• Auxiliary Processor Unit (APU) controller to integrate hardware accelerators and create custom co-processors
• Non-blocking pipelined point-to-point access to TEMAC, PCIe blocks, and FPGA logic
• Dedicated memory interface port for up to 128-bit data transfer per cycle to offload PLB
• Highly pipelined transmit and receive scatter-gather DMA channels to maximize data transfer rates
• User selectable port prioritization and operating frequencies to optimize system performance
• CPU-intensive operations such as video and 3D data processing, and floating-point math can be offloaded
• Optimized hardware/software partitioning maximizes FPGA utilization and minimizes hardware cost
• Double/single-precision arithmetic operations using IEEE 754-compatible FPU option

Figure 1

PowerPC 440 processor embedded block

Figure 2

PowerPC 440 processor system design example

System monitor and analog-to-digital converter to simplify system management and diagnostics

This integrated solution for thermal management and the measurement of on-chip power supply voltages enables debug and testing during hardware development and manufacturing. User defined alarms warn of critical temperature or power supply conditions.

System Monitor is fully accessible from fabric or JTAG TAP, and functional on power up before FPGA configuration and during power down (via JTAG TAP only).

The fully specified general purpose analogue-to-digital converter (ADC) can digitize on-chip analog sensor output and monitor up to 17 external analog inputs for environmental data. Automatic calibration and self check features ensure accurate, reliable measurements over a temperature range of -40°C to +125°C.

• Single-chip solution for monitoring supply voltages and temperature
• On-chip temperature measurement (±4°C)
• On-chip power supply measurement (±1%)
• Easy to use, self-contained
• Usable before, during, and after device configuration
• Basic operation requires no design effort.
• Autonomous monitoring of all on-chip sensors
• User programmable alarm thresholds for on-chip sensor
• Built-in, user-accessible 10-bit, 200-kSPS (kilosamples per second) ADC
• Automatic calibration of offset and gain error
• DNL = ±0.9 LSBs maximum
• Up to 17 external analog input channels supported
• 0V to 1V input range
• Monitor external sensors e.g., voltage, temperature
• General purpose analog inputs
• Auto chip power down if 125°C is detected on-chip (disabled by default)

Documentation

• System Monitor User Guide
• System Monitor FAQs

Webcasts

• Enhance System Reliability and Performance with the Virtex-5 System Monitor Function

Reference Designs

• System Monitor ML50X Demonstration using MicroBlaze and EDK

Articles

• How to Simplify Power Design Development and Evaluation for FPGA-based Systems
• Using the JTAG Chain for Accurate System and Intra-Die Power and Thermal Analysis
• Enhancing System Management and Diagnostics with the Virtex-5 System Monitor

Figure 1

System monitor

Sparse chevron packaging technology to keep system noise under control

Advanced sparse chevron packaging technology delivers significant system design benefits to reduce design cycles and system cost:

• Reduces inductive crosstalk by providing a low-impedance return path near every I/O pin.
• Reduces the number of external decoupling capacitors, reduces board layer count, and simplifies board design by encapsulating low-inductance, on-substrate bypass capacitors.
• Lowers inductance using continuous Power/GND planes.

Figure 1

Sparse chevron packaging

Enhanced configuration and bitstream protection to reduce system cost and increase reliability

To reduce system cost, increase reliability, and safeguard your design, you can use:

• SPI flash memory
• Parallel flash memory
• Xilinx platform flash devices

Enhanced bitstream management simplifies in-system reconfiguration and increases reliability with:

• Support for warm/cold FPGA boot as well as a safe bitstream if FPGA errors occur.
• Background CRC checking capability.

Advanced Encryption Standard (AES) security and battery-backed key

• AES bitstream encryption/decryption technology protects your IP with individually generated encryption key and encrypted bitstream. Incoming bitstreams are decrypted during configuration.
• Battery-backed (20+ year life) key provides unbreakable security for your design data. The encryption key is stored internally in dedicated RAM and cannot be read out of the device. Unlike non-volatile key storage methods, any attempt to remove the FPGA and decapsulate the package for probing results in the instant loss of the encryption key and programming data.