40nm ExpressFabric architecture with 6-input LUTs

Achieve highest performance with most efficient utilization on 40nm triple-oxide process.

Second generation ExpressFabric technology employs 6-input look-up tables (LUT) for higher performance through reduced number of logic levels, reduced routing, and lower fanout. For additional performance gains, Xilinx doubled the number of flip-flops associated with each LUT to better support pipelining of high-speed designs.

• 40nm triple-oxide process delivers one speed-grade higher performance, 50% lower power than previous generation
• Second-generation six-input look-up table (LUT) architecture enhances pipelining with highest flip-flop:LUT ratio
• Flexible LUTs are configurable as logic, distributed RAM (64 bits per LUT / 256 bits per CLB) or shift registers
• Second-generation diagonally symmetric interconnect enables shortest, fastest routing
• From 74,500 to 758,800 logic cells for system-level integration

600MHz clock management tiles (2 MMCM)

Achieve highest speeds with high-precision, low-jitter clocking.

New mixed-mode clock managers (MMCM) in Virtex-6 FPGAs deliver the benefits of flexible, precise clock synthesis, phase shifting, and jitter filtering provided by the DCM and PLL circuits in the device's clock management tiles (CMT). Enhanced clock distribution networks employ new mid-point buffering to reduce skew.

• New PLL-based mixed-mode clock managers (MMCM) for lowest jitter, jitter filtering
• Improved frequency synthesis offers 8x finer control
• Same fine phase control as provided by Virtex-5 DCM technology
• 18 MMCMs provide precise phase control of less than 30 ps for better design margin
• Differential global and regional clocking ensures low skew and jitter
• Mid-point buffering reduce skew and jitter in on-chip clock network

600MHz block RAM (1,000Kbits)

600MHz, 36 Kbit block RAM for high-density on-chip memory for efficient data buffering.

Virtex-6 FPGAs offer up to 38Mbits of integrated block RAM for buffering and storing data on chip. Flexible block RAM can be configured as two 18Kb blocks or a single 36Kb block, true dual-port, simple dual-port, and FIFO, and offers independent read and write port width configuration. Achieve 600MHz operation using optional pipeline capability. Built-in cascade logic makes it possible to create a 64k x 1 memory from two 32k x 1 block RAM configurations.

• Split into two 18 Kbit blocks to double Block RAM bandwidth
• Configure block RAM as multi-rate FIFO
• Built-in 64-bit error-correcting code (ECC) function for high-reliability systems
• Automatic power conservation circuitry

1.40Gbps SelectIO with ChipSync source-synchronous technology

Implement industry-standard and custom protocols.

Built-in capabilities make it easy to meet the toughest timing requirements for industry-standard and custom protocols, while supporting multiple electrical standards in the same device with 30 individually configurable I/O banks.

• Design with PCI®, RapidIO™, XSBI, SPI4.2, and more
• Configure I/Os to support HSTL, LVDS (SDR and DDR), and more, at voltages from 1.0V to 2.5V
• Interface to popular standards with 1.40Gbps differential and 1,066+ Mbps single-ended I/O
• Simplify board design with built-in I/O delay circuits that compensate for unequal trace lengths with flexible per-bit deskew
• Synchronize incoming data to FPGA internal clock with built-in Serializer/ Deserializer
• Built-in support for DDR3 memory
  • Write leveling
  • Dynamic clock inversion control
  • Low jitter performance path clocking
• Adaptive delay setting recalibrates automatically to compensate for changing operating conditions
• Three-statable digitally controlled impedance reduces power for memory interfaces, shrinks component count and board size
• Digitally-Controlled Impedance (DCI) with on-chip active I/O termination reduces component count, saves board space, and simplifies board design
• New performance path clocking networks provide dedicated paths to reduce jitter for off-chip clocking

6.5Gbps GTX transceivers

Achieve low-power connectivity with line rates between 150Mbps and 6.5Gbps

Implement serial protocols at the lowest power to build complete serial solutions for chip-to-chip, board-to-board, and box-to-box communications quickly and easily.

• Flexible SERDES enables transmit and receive paths to operate at different data rates, effectviely doubling the number of transceviers for certain applications
• Powerful transmit and receive equalization (transmit pre-emphasis, receive linear equalization, and DFE) for best signal integrity at high line rates
• Integrated “gear box” for flexible encoding: 8b/10b, 64b/66b, 64b/67b
• Highly flexible clocking enables independent Rx and Tx operation to effectively double the number of transceivers available for certain applications
• Designed to work with integrated PCI Express and tri-mode Ethernet MAC blocks
• 25% lower power consumption: <15 mW (typ) at 6.5Gbps
• Obtain assured compliance with popular standards such as 10/40/100G Ethernet, PCI Express,OC-48, XAUI, SRIO, and HD-SDI

>11Gbps GTH transceivers

GTH Transceivers: 9.953Gbps - >11Gbps

Implement the highest performance serial protocols with complete serial solutions for building chip-to-chip, board-to-board, and box-to-box communications quickly and easily.

• Flexible SERDES supports multi-rate applications
• Enables 40G and 100G protocols and more
• Powerful transmit and receive equalization (transmit pre-emphasis, receive linear equalization, and DFE) for best signal integrity at high line rates
• Integrated “gear box” for flexible encoding: 8b/10b, 64b/66b
• Low power consumption: ~220mW (typ) at 10.3125Gbps
• Obtain assured compliance with popular standards such as 1/40/100G Ethernet, PCI Express,OC-48, XAUI, SRIO, and HD-SDI

PCI Express (Gen1) Endpoint/Root Port blocks

Implement PCI Express with reduced cost, power, and complexity.

Minimize design risk with integrated PCIe interface blocks for building next-generation graphics, storage, networking, and I/O devices. The PCI Express block in Virtex-6 FPGAs implements transaction layer, data link layer, and physical layer functions to provide complete PCI Express endpoint and root-port functionality with minimal FPGA logic utilization.

• PCI SIG-verified Gen1 and Gen2 compliance (on integrators list)
• Works with GTX transceivers to deliver PCIe endpoint and root port function
• Built-in hard IP frees user logic resources and reduces power
• Multiple PCIe blocks for increased bandwidth, multiple functions, or simultaneous implementation of endpoint and root port support in a single FPGA
• Preserve software investment and extend infrastructure life with scaleable bandwidth (x1, x2, x4, x8 at Gen1 and Gen2 data rates)
• Re-target designs to larger FPGAs without changing your PCIe interface implementation as your project evolves

Ethernet Media Access Controller blocks

Connect to the Internet via an integrated tri-mode EMAC.

Virtex-6 FPGAs incorporate four embedded tri-mode Ethernet media access controller (MAC) blocks (with the exception of the Virtex-6 LX760 device) to provide flexible connectivity while freeing user logic resources and reducing power consumption. 10/100/1000 Mbps tri-mode EMAC capabilities are IEEE 802.3 compliant and UNH-interoperability tested and certified. They offer:

• 2.5 Gbps mode for higher bandwidth using custom protocols
• Programmable PHY Interface
• MII/GMII with SelectIO interface
• SGMII when used with RocketIO™ transceivers (requires external phy)
• Real-time statistics interface ports for performance monitoring of both Tx and Rx frames
• Jumbo frames support
• Receive address filter to accept/reject packets
• DCR-bus connection to microprocessors
• Complete single-chip solution for 1000 Base-X when using RocketIO transceivers (no external phy required)
• Ideal for network management or remote FPGA monitoring
• User configurable interface

600MHz DSP48E1 slices

Up to 900+ GMACS performance using DSP48E1 slices to increase algorithm performance.

Achieve 1,000 GMACS performance using DSP48E1 slices to build efficient hardware implementations of filters that leverage the parallelism inherent in the FPGA architecture.

• Increased DSP resources in all devices; up to 2,016 slices in a Virtex-6 SX475T FPGA
• Enhanced architecture with a 25 x 18 multiplier, 48-bit adder, and 48-bit accumulator (cascadable to 96 bits) enables single and double-precision floating-point math and high precision filters with fewer slices
• New integrated pre-adder implements more efficient, higher-performance symmetric and polyphase filters
• Support for pattern detection, convergent rounding, and underflow/overflow detection for saturation arithmetic
• Over 40 dynamically controlled operating modes including multiplier, multiplier-accumulator, multiplier-adder/subtractor, three input adder, barrel shifter, wide bus multiplexers, wide counters, and comparators
• Low power consumption: each DSP48E1 slice draws only 1.09mW/100MHz at a 38% toggle rate, a 20% reduction from previous-generation slices

System monitor and analog-to-digital converter

Simplify system management and diagnostics.

This integrated solution for thermal management and the measurement of on-chip power supply voltages simplifies system management and diagnostics and can be used to minimize power consumption. System Monitor also enables debug and testing during hardware development and manufacturing. User defined alarms warn of critical temperature or power supply conditions.

System Monitor is fully accessible from fabric or JTAG TAP, and functional on power up before FPGA configuration and during power down (via JTAG TAP only). The fully specified general purpose analogue-to-digital converter (ADC) can digitize on-chip analog sensor output and monitor up to 17 external analog inputs for environmental data. Automatic calibration and self check features ensure accurate, reliable measurements over a temperature range of -40°C to +125°C.

• Single-chip solution for monitoring supply voltages and temperature
  • On-chip temperature measurement (±4°C)
  • On-chip power supply measurement (±1%)
• Easy to use, self-contained
  • Usable before, during, and after device configuration
  • Basic operation requires no design effort
  • Autonomous monitoring of all on-chip sensors
  • User programmable alarm thresholds for on-chip sensor
• Built-in, user-accessible 10-bit, 200-kSPS (kilosamples per second) ADC
  • Automatic calibration of offset and gain error
  • DNL = ±0.9 LSBs maximum
• Up to 17 external analog input channels supported
  • 0V to 1V input range
  • Monitor external sensors e.g., voltage, temperature
  • General purpose analog inputs
• Auto chip power down if 125°C is detected on-chip (disabled by default)

Third-generation sparse chevron packaging technology

Keep system noise under control and simplify PCB layout.

Advanced sparse chevron packaging technology delivers significant system design benefits to reduce design cycles and system cost.

• Unique PWR/GND pin pattern minimizes crosstalk and reduces PCB layers
• On-substrate bypass capacitors shrink PCB area

Enhanced configuration and bitstream protection

Reduce system cost, increase reliability, and safeguard your design.

• Configure with commodity SPI and parallel flash memory
• Partial reconfiguration support for increased design flexibility and logic efficiency; now 10x faster
• Reliable in-system reconfiguration with multi-bitstream management
• Built-in error detection and correction for better SEU protection
• Protect your designs with 256-bit AES (Advanced Encryption Standard) security with battery-backed or non-volatile e-fuse key storage
• Device DNA enables protection against unauthorized overbuild