Xilinx Press Release #02110

FOR IMMEDIATE RELEASE 

XILINX EXTENDS LEAD IN SYSTEM CONNECTIVITY, SHIPS INDUSTRY'S FIRST COMPLETE RAPIDIO ENDPOINT CORE
Company to demonstrate and discuss FPGA-based solution at Motorola's
Smart Networks Developer Forum

SAN JOSE, Calif., July 15, 2002-Xilinx, Inc. (NASDAQ: XLNX) today announced its new RapidIO™ Logical and Transport layer Intellectual Property (IP) core for use with the company's flagship Virtex®-II series Platform FPGAs. This core, when combined with the industry's first RapidIO physical layer core available from Xilinx since May 2001, form a complete RapidIO endpoint solution that can be used to build switch cards for communication and storage equipment, interface to control plane and network processors, DSP farms, and bridges to legacy buses and proprietary and standards-based backplanes. For complete information about the RapidIO core, visit http://www.xilinx.com/systemio.

"The Xilinx solution brings the promise of RapidIO into reality and allows system architects to start building their next generation systems right away," said Sam Fuller, president of the RapidIO Trade Association. "RapidIO is quickly gaining acceptance as the interconnect of choice for major networking and telecommunication infrastructure companies due to its reliability, scalability and support from a large base of processor, ASSP and programmable logic vendors."

"As a result of the constant change in the I/O standards landscape, FPGAs are expected to play a key role in the future of high-performance communications and networking systems," said Mark Aaldering, senior director of the IP solutions division at Xilinx. "The RapidIO cores from Xilinx are yet another industry first, demonstrating our commitment to provide our customers with complete solutions for building high performance, scalable and reliable communications equipment."

Next week, Xilinx will demonstrate the RapidIO endpoint solution at Motorola's Smart Networks Developer Forum (SNDF), held in New Orleans, Louisiana from July 21 through 24. Two Xilinx Virtex-II Platform FPGAs are used to implement two distinct RapidIO cores connected across a cable. Conference attendees can view multiple data packets being sent from one core to the other across the cable at the rate of 4 Gbps in each direction on a liquid crystal display. The company will also participate in a panel discussion focused on RapidIO being held on Tuesday, July 23, 2002 at SNDF. Senior Director Aaldering will represent Xilinx.

RapidIO Endpoint
The RapidIO endpoint solution uses special features of the Virtex-II series FPGAs, such as the BlockRAM, Digital Clock Managers and the 840 Mbps LVDS I/Os, to support an aggregate bandwidth of up to 8 Gbps per port. It supports both initiator and target transactions and six separate user ports with independent flow control, including a dedicated maintenance port. It has a 64-bit internal data path and supports packet retry, time-of-day sync, stomp, transmission error recovery, throttle based flow control and CRC.

The Ultimate Connectivity Platform
Today's news underscores the company's commitment to provide customers with the ultimate connectivity platform and interface solutions for tomorrow's networking and communication designs. As part of the Xilinx Platform FPGA SystemIO solution, the company continues to deliver a wide-range of leading parallel and serial connectivity solutions.

License price and availability
The RapidIO physical, and logical and transport layer cores are fully compliant with RapidIO Interconnect Specification v1.1and available now from Xilinx as LogiCORE™ products under the terms of the SignOnce license agreement. Once purchased, they can be downloaded online at http://www.xilinx.com/rapidio. The site license for the physical layer core is priced at $15,000 and for the logical and transport layer core at $10,000. Both cores support Xilinx Virtex-II FPGAs using the latest ISE 4.2i design software.

About Next Week's Metro-Optical Networking Forum
Xilinx, along with other industry leaders, will also host a free one-day event on July 25, 2002 in Santa Clara, Calif. The all-day event is the first to address the challenges of designing and developing products for the metro area and edge access networks. Attendees will hear first hand from industry experts on where this dynamic market is headed, as well as the technologies driving success in the MAN space. Xilinx will be showcasing its RapidIO demo at the event. For complete agenda and registration information, visit www.xilinx.com/metro.

About Xilinx
Xilinx, Inc. (NASDAQ: XLNX) is the worldwide leader of programmable logic solutions. Additional information about Xilinx is available at www.xilinx.com.

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