FOR IMMEDIATE RELEASE

XILINX VIRTEX-II PRO FPGAS ENABLE XAUI DE-SKEW VALIDATION AT UNIVERSITY OF NEW HAMPSHIRE 10Gb ETHERNET INTEROPERABILITY GROUP TEST

Demonstrates advantages of combining programmable 3.125 Gbps serial transceivers and immersed PowerPC in Virtex-II Pro platform FPGAs

SAN JOSE, Calif., November 4, 2002 -Xilinx, Inc. (Nasdaq:XLNX) today announced that the company successfully provided a skew insertion design using its flagship Virtex-II ProÔ FPGAs with the unique combination of embedded 3.125Gbps serial transceivers and immersed PowerPC processors in the October University of New Hampshire's Interoperability Lab XAUI Group Test. The solution allowed the verification of industry XAUI standard implementations. Xilinx provided a design to probe the XAUI receiver of each device under test with standard test patterns containing variable skew across all four 3.125Gbps lanes of the XAUI interface. This allows system engineers to easily measure device de-skew capability to ensure reliable 10 Gigabit Ethernet backplane and data plane designs.

"Demonstrating the speed from concept to design and the high-performance capability and programmability of the Virtex-II Pro FPGAs, Xilinx quickly delivered a solution to generate controllable XAUI lane-to-lane skew with a bit-level granularity," said Bob Noseworthy, 10 Gigabit Ethernet consortium manager at the University of New Hampshire. "This allowed us to test vendor's compliance with the IEEE 802.3ae specification down to the last Unit Interval of skew. As such, we were easily able to verify that the tested devices met or exceeded the required de-skew tolerance and confirmed to the vendor's de-skew capability. As XAUI technology extends into longer channels and new environments, such as shielded copper cabling, the need to precisely measure a device's de-skew capability will only increase."

"Providing the skew insertion design was an ideal application using the embedded PowerPC processor and serial transceivers in the Virtex-II Pro device and our own XAUI core," said Mark Aaldering, senior director of IP Solutions at Xilinx. "The test patterns stored in Block RAM could be easily manipulated in software by using PowerPC to control the output delays which are provided by the SRL16 shift registers on a per lane basis."

Designers can easily implement the XAUI interface by channel bonding four Virtex-II Pro RocketIO™ transceivers to send and receive serial data at a total baud rate of 12.5 Gbps. The RocketIO transceivers also provide the necessary 8B/10B encode/decode circuitry for symbol insertion and extraction on each lane, and a designer can utilize the fabric for efficient processing of the data and flexible interfacing to the core. Xilinx provides ready to use 10Gigabit MAC with XAUI core as part of the comprehensive system connectivity solutions. For details on this core, visit www.xilinx.com/connectivity

About High-Speed Serial Initiative
The Xilinx High-Speed Serial Initiative, announced October 21, 2002 is designed to accelerate the industry move from parallel to serial I/O technology by delivering next generation connectivity solutions that meet bandwidth requirements from 3.125 Gbps today to 10 Gbps and beyond. For complete information about the High-Speed Serial Initiative, visit www.xilinx.com/serialsolution.

About Xilinx
Xilinx, Inc. (NASDAQ: XLNX) is the worldwide leader of programmable logic solutions. Additional information about Xilinx is available at www.xilinx.com.

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Editorial contact:

Jennifer Van Every

Xilinx Public Relations

(408) 879-7727

jennifer.vanevery@xilinx.com