FOR IMMEDIATE RELEASE

XILINX PROVIDES UNPRECEDENTED SYSTEM INTEGRATION
WITH NEW DUC AND ENHANCED FEC DSP CORES

SAN JOSE, Calif. - December 24, 2003 - Xilinx, Inc. (NASDAQ:XLNX) today announced the immediate availability of a Digital Up Converter (DUC) LogiCORETM module for digital communication system design. The new core, that is included with the Xilinx ISE software, enables customers to reduce system cost by integrating multiple DUC cores into a single FPGA. Xilinx also announced enhanced forward error correction (FEC) cores, such as a Reed-Solomon solution supporting ITU-T J.83 variable block length and multi-channel capability and an enhanced convolutional Interleaver core supporting selectable configurations on-the-fly. Additionally, the CDMA2000/3GPP2 Turbo Convolutional Codec (TCC) solution, announced as a beta product in July 2003, is now available as a production solution. These cores, which are used extensively in wireless and wireline communication systems, further extend Xilinx's DSP IP offering.

"With the release of the new DUC core and the enhanced FEC cores, the Xilinx DSP solution provides everything from base-band processing to generating signals for the digital IF," said Chris Dick, chief DSP architect at Xilinx. "Integrating all of this functionality on an FPGA provides designers with maximum flexibility while reducing cost."

New Digital Up Converter
The new DUC core provides a highly flexible solution for applications such as software defined radios, digital transmitters, cable modems, BPSK, QPSK and QAM modulators, spread spectrum communication systems, and CDMA2000 and 3G basestations. Key features include:

• Diverse range of interpolation rates (5 to 5792)
• Local oscillator spurious free dynamic range of 115 dB
• Multi-stage, multi-rate design enabling designers to select filter lengths between 4 and 1024 taps and define coefficient precision between 4 and 32 bits
• Designed for use with the Xilinx System GeneratorTM for DSP software platform

Learn more at http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DUC.

Availability
All of these cores are available now from Xilinx at: www.xilinx.com/dsp. The DUC is included with the latest version of the Xilinx CORE GeneratorTM System. The Reed-Solomon, Interleaver and TCC cores are available as separately licensed parameterized netlists. Full system hardware evaluation versions of the Reed-Solomon and Interleaver cores are available at www.xilinx.com/ipcenter/ipevaluation/index.htm. All of the cores support the latest Xilinx Virtex and Spartan Series FPGAs and ISE 6.1I design software.

Xilinx XtremeDSP Initiative
Today's announcement represents another major milestone in the Xilinx XtremeDSP initiative and further extends the company's leadership position in high performance, easy to use DSP solutions. Xilinx's commitment to DSP technology resulted in the company's XtremeDSP initiative over three years ago.

Through its XtremeDSP initiative, Xilinx has already delivered a wide range of solutions:

• Virtex -II and Virtex-II Pro FPGAs: World's first platform FPGAs with dedicated DSP features with up to 556 embedded 18x18 multipliers and over 10 megabits block and distributed memory.
• Spartan-3 FPGAs: World's first and only low cost FPGA family built on a 90nm process with dedicated DSP functions, such as 104 embedded 18x18-bit multipliers & 2 megabits of block RAM
• First to market with familiar DSP design methodologies resulting from strategic partnerships with The MathWorks.
• Extensive library of proven DSP IP cores and advanced development boards to accelerate the design cycle and maximize performance.
• Wealth of design resources including design services, dedicated field specialists, and DSP education classes.
  

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Editorial contact:

Jennifer Wright Van Every

Xilinx Public Relations

(408) 879-7727

jennifer.vanevery@xilinx.com