FOR IMMEDIATE RELEASE

Hier Design PlanAhead Software Provides Substantial Time-to-Market Advantage with Xilinx ISE 6.1i
Speeds Physical Implementation through ASIC-Like Design Methodology

SANTA CLARA, Calif., September 9, 2003 - Electronic Design Automation (EDA) Software Supplier Hier Design Inc. announced today that its PlanAhead™ hierarchical floorplanning and analysis software offers full support for the latest version of the Xilinx Inc. (NASDAQ: XLNX) Integrated Software Environment 6.1i (ISE).

The combination of ISE 6.1i and the PlanAhead software gives users of Xilinx Virtex-II™ and Spartan-3™ device families an ASIC-like flow for the design of field programmable gate arrays (FPGAs). Customers benefit from a proven methodology for reducing place and route time, the number of design iterations, and the time needed to achieve timing requirements.

Hier Design provides advanced floorplanning and integrated analysis capabilities to identify and correct potential routing congestion, utilization, timing and other problems early in the design cycle, where they are easier and faster to fix.

"Through the integration of ISE 6.1i and our PlanAhead software, FPGA designers have a tool flow that's virtually indistinguishable from an ASIC design flow, and get similar flexibility and productivity enhancements," remarks Salil Raje, Hier Design's chief technology officer (CTO).

The PlanAhead software shortens the design cycle by providing a faster, less iterative path from logic synthesis through physical design while reaching and maintaining design performance goals. Its advanced analysis capability enables designers to more easily comprehend, modify, verify and implement their Xilinx FPGAs.

"Hier Design's PlanAhead software provides a unique FPGA design solution which will help enable the further growth of the FPGA market," adds Jerry Banks, director of Global Alliances at Xilinx. "Our development groups have worked closely together to ensure the tightest possible integration and deliver a design flow with unmatched high-speed design capabilities and ease-of-use floorplanning features."

Contacting Hier Design
For more details on the PlanAhead hierarchical floorplanning and analysis software, contact Dino Caporossi, vice president of marketing at Hier Design. He can be reached at (408) 982-8257 or via email at dino@hierdesign.com. More details about the PlanAhead software can be found at: http://www.hierdesign.com.

About ISE 6.1i
With over 31 percent better performance and up to 60 percent cost savings over competing solutions, Xilinx ISE 6.1i is the world's highest performance software for programmable logic. ISE 6.1i sets the industry standard for ease of use, solves traditional design bottlenecks to speed design and verification, and dramatically reduces customer's overall design cycle time and design costs. The software suite, coupled with Xilinx Virtex-II Pro and Spartan-3 FPGAs offering breakthrough price points, device densities, and performance, offer designers an ideal ASIC replacement solution. For information about ISE 6.1i, visit www.xilinx.com/ise.

About Hier Design
Founded in 2001, Hier Design Inc. is an electronic design automation (EDA) industry newcomer creating the next EDA beachhead by helping fuel the movement from application specific integrated circuits (ASICs) to high-speed, highly complex field programmable gate arrays (FPGAs). It has raised a total of $6.2 million in financing since it was founded in 2001 from ITU Ventures, Xilinx Inc. (NASDAQ: XLNX), Cadence Design Systems Inc. (NYSE: CDN), Innotech Corporation, Lanza Tech Ventures and private investors. Corporate headquarters is located at: 2350 Mission College Boulevard, Suite 850, Santa Clara, Calif. 95054. Telephone: (408) 982-8240. Facsimile: (408) 982-3838. Email: info@hierdesign.com. More details can be found at the Hier Design website located at: http://www.hierdesign.com.

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