FOR IMMEDIATE RELEASE

XILINX ANNOUNCES SUCCESSFUL INTEROPERABILITY
BETWEEN XILINX AND IBM HIGH SPEED SERDES TECHNOLOGY
Xilinx ensures compatibility between IBM ASICs and Xilinx Virtex-II Pro FPGAs

SAN JOSE, Calif., December 22, 2003 - Xilinx, Inc. (NASDAQ: XLNX) today announced successful interoperability testing of the IBM High Speed SERDES (HSS) core with Xilinx's Virtex-II Pro 3.125 serial transceivers. With Xilinx FPGAs and IBM ASICs often on the same boards, the interoperability testing significantly reduces overall product time-to-market by allowing customers to focus on design issues rather than verifying electrical compliance. Applications now enabled include high-speed interface requirements for Fibre Channel, PCI Express, Serial Rapid I/O, Serial ATA, Serial Attached SCSI, 10Gb Ethernet, and OIF interfaces.

"The interoperability of the IBM and Xilinx SERDES cores, coupled with Xilinx's industry standard interface compliance is a testament to the robustness of the two company's SERDES designs," said Bill Van Duyne, director of Field Applications for IBM Microelectronics. "IBM ASIC customers will find that not only do Xilinx FPGAs lend themselves to needed board logic, they can also extend ASIC product life-cycles given their flexibility which allows additional functionality to be added later."

"IBM SERDES interoperability with Xilinx high-speed serial transceivers is key to ensuring the confidence of designers who need to add the flexibility of a Xilinx FPGA to complement their ASIC design," said Jerry Banks, director of Global Alliances at Xilinx. "Interoperability testing now reduces the need for interoperability testing later in the design cycle."

The test and verification interoperability plan was designed to ensure full and rigorous electrical interoperability testing of the two cores. Both SERDES technologies were tested interactively for transmit and receive functions. Additionally, the signaling was performed asynchronously in order to most faithfully reproduce an actual functional environment. A variety of pseudorandom test patterns were used in order to mimic actual data traffic. Furthermore, both backplane and point-to-point signaling were characterized. In the end, no bit errors were logged between the two devices in any of the test cases.

IBM HSS Core
The IBM High Speed SERDES family-of-cores support data throughput rates from 125 Mbps to 6.4Gbps. With sophisticated equalization circuitry and the ability to implement up to 200 links on a single chip, a single IBM ASIC in 0.13um can support 2.5 Tbps of effectively error - free transmission for all popular high-speed serial transmission standards. For more information on this and other IBM Blue Logic ASIC offerings, go to http://www-3.ibm.com/chips/products/asics.

Xilinx Reference Design Alliance Program
The Xilinx Reference Design Alliance Program (www.xilinx.com/reference_design) builds collaborations with industry leading semiconductor and design companies to develop reference designs for accelerating our customer's product and system time-to-market. IBM is a member of the Xilinx Reference Design Alliance Program.

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Editorial contact:

Jennfier Wright Van Every

Xilinx Public Relations

(408) 879-7727

jennifer.vanevery@xilinx.com