FOR IMMEDIATE RELEASE
XILINX SPARTAN-3 DEVICES ENABLE HIGH PERFORMANCE
DSP FUNCTIONS AT BREAKTHROUGH LOW COST PRICE POINTS
Company delivers a 32-channel Viterbi decoder core for communication
subsystems for $0.14* and DUC/DDC functions for wireless base stations
at $2.22* per channel
SAN JOSE, Calif., December 10, 2003 - Representing a major milestone
in the FPGA-based DSP space, Xilinx Inc. (NASDAQ: XLNX) today announced
revolutionary low cost price points for high performance DSP functions.
DSP functions used in communications subsystems such a FEC 32-channel
Viterbi decoder core** can now be implemented in a Spartan-3 FPGA
(XC3S1000) for an effective price of $0.14 per channel. Digital
up and down conversion (DUC and DDC) running at 100 MSPS - common
functions used to modify the received/transmitted frequencies in
wireless base stations - can also be implemented for an effective
price of $2.22* per channel.
The low cost Spartan-3 family - the first and only FPGA using a
90nm process - is the only FPGA in its class with dedicated DSP
functionality. Combined with pre-verified IP cores for implementing
complex DSP algorithms, the Spartan-3 family is driving down the
cost of high performance DSP used in a wide range of digital video
technology, digital consumer, computing and wireless systems.
"Given the Spartan-3 family's unrivalled cost structure and
architecture tuned for DSP applications, designers now have a low-cost
programmable logic option when implementing DSP functions,"
said David Squires, director of the DSP Center of Excellence at
Xilinx. "Embedding DSP functions in a low cost FPGA at these
price points opens up a whole new range of applications for programmable
logic in the exploding markets for digital consumer and wireless
Xilinx benchmarks also show that functions commonly used by DSP
system designers such as a 1024 point FFT*** (with 20 micro-seconds
transform time) can be implemented in a Spartan-3 device at an effective
price of $2.72*. A single channel, 64-tap FIR filter**** running
at 8.1 MSPS can be implemented for an effective cost of $0.36*.
These are common DSP functions that are used in a wide range of
applications such as plasma displays, medical imaging, base-stations
and wireless infrastructure products.
Recognizing the prevalence of DSP functions in today's systems,
Xilinx designed the Spartan-3 architecture with features that enable
customers to implement DSP functions efficiently and cost effectively
within the FPGA fabric - allowing higher integration and lower system
costs. Some of the unique features of the Spartan-3 architecture
- Up to 104 18x18-bit embedded multipliers. These can be used
to implement compact DSP structures such as MAC engines, FFTs,
and fully parallel FIR filters.
- SRL16 shift register logic for implementing shift registers
and multiple channel functions.
- Distributed memory for building compact DSP structures such
as FIFOs and filters.
Xilinx provides an extensive library of intellectual property cores
that enable designers to implement complex DSP algorithms, such
as FEC codecs, filters and transform fucntions for digital communication
and imaging applications. All DSP cores are designed to yield the
fastest and smallest implementations in the FPGA industry. Many
of these IP cores are included in the Xilinx System Generator for
DSP system level tool for implementing DSP on FPGAs. A free XtremeDSP
Software Evaluation CD Kit, which includes the System Generator
for DSP tool, is available at: www.xilinx.com/dsp/eval_software.htm.
Spartan-3 - World's Lowest Cost FPGA Platform
The combination of the advanced process and staggered I/O pad technology,
gives Spartan-3 devices the lowest cost per logic cell (CPL) as
well as the lowest cost per I/O (CPI); making them essential in
developing leading-edge systems at affordable pricing. Starting
at $2.95*, the Spartan-3 family addresses customer demand for low
cost solutions and significantly expands the total available FPGA
market. The Spartan-3 platform builds upon the proven success over
four generations of Spartan Series solutions. Since its 1998 introduction,
the company has shipped more than 60 million Spartan Series devices.
Pricing and Availability
The 3S50, 3S200, and 3S400 Spartan-3 devices with 50,000, 200,000,
and 400,000 system gates respectively, sells for less than $6.50*.
The 3S1000 Spartan-3 device with 1 million system gates also sells
for under $12.00*. The entire Spartan-3 family will be available
in volume production in early 2004 from distributors worldwide or
direct from Xilinx at www.xilinx.com/spartan.
Xilinx Global Services
Designers can learn how to effectively implement DSP functions while
taking advantage of the other features available within Spartan-3
through several Xilinx Education Services courses, including two
specifically focused upon DSP design. In addition, a variety of
other services ranging from consultative, dedicated, to technical
support services and tools for DSP are available today. For more
information, please visit the DSP Services and Training section
of DSP Central www.xilinx.com/dsp. For additional information on
Xilinx Global Services, reference www.xilinx.com/services.
Xilinx is the worldwide leader in complete programmable logic
solutions. For more information, visit www.xilinx.com.
* Based on volume pricing for 250K units, end of
** Parallel mode Viterbi Decoder core (traceback 42, constraint
length 7, 32 channel, 1.9 MSPS per channel)
*** 1024-point complex FFT core (20 micro-second transform time,
burst I/O, 16-bit input, and phase factor)
**** Single channel 64-tap FIR filter core (MAC implementation,
16-bit data and coefficients, 8.1 MSPS)