FOR IMMEDIATE RELEASE

XILINX PLANAHEAD V2.2 TOOL DELIVERS UP TO 2X PERFORMANCE BOOST AND 50% DESIGN CYCLE REDUCTION FOR VIRTEX-4 FPGAs

New release of PlanAhead floorplanner now supports Virtex-4 devices,
the industry's highest density, highest speed FPGA family shipping on 90nm technology

SAN JOSE, Calif., January 12, 2005 - Xilinx, Inc. (NASDAQ:XLNX) today announced the immediate availability of its next generation PlanAheadTM v2.2 FPGA hierarchical floorplanning and design tool. The PlanAhead v2.2 tool fully supports the company's Virtex-4 family - already the industry's fastest FPGAs with up to 43% higher logic performance over competing solutions. FPGA designers can now further boost logic performance of Virtex-4 design by up to 2X with the PlanAhead block-based implementation flow. In addition, the PlanAhead methodology has shown to reduce overall design closure times on several customer designs by 50%.

The PlanAhead system is employed between synthesis and place & route enabling designers to implement a block-by-block implementation approach. The tool adds functionality to help Virtex-4 designers rapidly analyze, modify and achieve superior performance on each of the blocks. Blocks can then be stitched together in a final assembly phase.

"We are pleased to see that our high-density customers continue to adopt the PlanAhead approach because of the dramatic performance improvements they can achieve. High-density customers are typically large teams of designers working on a single device. The block-based incremental methodology enabled by our PlanAhead product dramatically shortens turn-around times for design teams as well," said Rich Sevcik, executive vice president of the FPGA Products Group at Xilinx.

The PlanAhead v2.2 release comes with improved support for block-based timing analysis. The ability to view and edit constraints has been tightly integrated into the design environment. This enables the designer to try different "what-if" scenarios on their blocks without having to experience unnecessary place & route runs. The PlanAhead floorplanning methodology also allows designers to maneuver the complexities of Virtex-4 architectures through its analysis and estimation capabilities. Design rule checks have been added to ensure optimal use of the DSP and RAM blocks within Virtex-4 devices. Support for rectilinear floorplan regions has been added to account for discrete and disparate macro resources within the FPGA fabric. All together, the PlanAhead floorplanner has become the preferred environment for high-density FPGA designers. The hierarchical design methodology that PlanAhead solution brings to the Xilinx design flow has no parallel in the FPGA design tools domain.

Pricing & Availability
The PlanAhead v2.2 solution is immediately available for use with the Integrated Software Environment (ISE) 6.3i FPGA design suite from Xilinx. The tool is priced at $15,000. For more information about the latest version of this tool, visit http://www.xilinx.com/planahead. For more information on the PlanAhead hierarchical floorplanner contact: fpga@xilinx.com.

About Xilinx Virtex-4 Platform FPGAs
Enabled by the revolutionary ASMBL (Advanced Silicon Modular Block) architecture and advanced 90nm triple-oxide technology, Virtex-4 FPGAs deliver more options, higher performance and lower power than any other FPGA family available today. With more than 100 technical innovations, the Virtex-4 family consists of 17 devices and three domain-optimized platforms; Virtex-4 LX FPGAs optimized for logic-intensive designs, Virtex-4 SX FPGAs optimized for high-performance signal processing, and Virtex-4 FX FPGAs optimized for high-speed serial connectivity and embedded processing. A multi-platform approach makes it possible for customers to select the optimal mix of resources for their application to achieve the highest functionality and breakthrough performance at the lowest cost. Devices are shipping now. For more information on the Virtex-4 product family, visit www.xilinx.com/virtex4.

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