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Xilinx Press Release #0363

FOR IMMEDIATE RELEASE

Hier Design Supports Xilinx's New 90nm Spartan-3 FPGAs With Silicon Virtual Prototyping Solution to be Introduced in July

New Tool to Serve the Needs of Sophisticated FPGA Designers

SANTA CLARA, Calif., April 28, 2003 - Hier Design Inc., headquartered here, today announced its full support of Xilinx Inc.'s (Nasdaq: XLNX) new class of 90nm Spartan® field programmable gate array (FPGA) solutions - the Spartan-3 platform.

Hier Design, a Xilinx AllianceEDA partner, offers a family of silicon virtual prototyping software to serve the needs of the sophisticated FPGA designer. The pre-release software, which supports Spartan-3 FPGAs, is being used at several beta customer sites. Currently the software products run on Windows, Linux, and Sun Solaris Unix-based workstations. Products initially will support Xilinx devices only.

Remarks Jackson Kreiter, Hier Design's chief executive officer and chairman: "Xilinx's Spartan-3 devices have the complexity, performance and affordability to obsolete ASICs in a large number of high-volume commercial applications. Designers are now demanding ASIC-style hierarchical design tools to efficiently utilize these complex devices, and we are excited to be the first vendor on the market that is providing such tools."

"The Hier Design family of silicon virtual prototyping solutions will quickly become a valued design tool set for Spartan-3 FPGA designers," adds Jerry Banks, director of Global Alliances at Xilinx. "Its capabilities will help Spartan-3 users gain a higher level of packing optimization for their design, resulting in a lower cost of implementation ¾ a critical benefit for today's system developers."

About Hier Design
Founded in 2001, Hier Design Inc. is an electronic design automation (EDA) industry newcomer creating the next EDA beachhead by helping fuel the movement from application specific integrated circuits (ASICs) to high-speed, high-complexity field programmable gate arrays (FPGAs). It will launch software in July 2003 that will enable programmable devices to obsolete ASIC technology for most standard products. Hier Design has raised a total of $6.2 million in financing since it was founded in 2001 from ITU Ventures, Xilinx Inc. (NASDAQ: XLNX), Cadence Design Systems Inc. (NYSE: CDN), Innotech Corporation, Lanza Tech Ventures and private investors. Corporate headquarters is located at: 2350 Mission College Boulevard, Suite 850, Santa Clara, Calif. 95054. Telephone: (408) 982-8240. Facsimile: (408) 982-3838. Email: info@hierdesign.com. More details can be found at the Hier Design website located at: http://www.hierdesign.com.

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