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FOR IMMEDIATE RELEASE
Click here for
the Virtex-4 Multi-Platform FPGAs Press Kit
XILINX SHIPS ISE 6.3i DESIGN SUITE,
WIDENS PERFORMANCE LEAD UP TO 40% WITH VIRTEX-4 FPGAs
New ISE release simplifies design for industry's
first multi-platform FPGAs, boosts overall tool performance and
expands low-cost design platform with support for Linux
SAN JOSE, Calif., September 13, 2004 - Xilinx, Inc. (NASDAQ: XLNX)
today announced immediate worldwide shipments of the 6.3i release
of its Integrated Software Environment (ISE), optimized for the
Xilinx Virtex-4 family of Platform FPGAs. The new ISE 6.3i solution
takes full advantage of the Virtex-4 architecture to support up
to 200,000 logic cells and 500 MHz performance for twice the density
and up to 10 times better performance-price ratio than previous
generation FPGAs. This combination of ISE 6.3i and Virtex-4 FPGAs
makes programmable systems design easier than ever across multiple
domains, including high performance logic, embedded processing,
high performance digital signal processing and high-speed connectivity.
The ISE 6.3i release also extends Xilinx leadership in proactive
timing closure and integration, while reducing overall design costs
for high-volume FPGA and CPLD applications. New easy-to-use, innovative
implementation options and third-party electronic design automation
(EDA) tool support are delivered with up to 40 percent faster FPGA
fabric performance than the nearest competing offering. ISE 6.3i
is also the most accessible design solution ever offered by Xilinx
with new availability for the Linux Red Hat Enterprise 3.0 operating
system.
"Designing at the performance levels and device densities that
we deliver in our Virtex-4 family demands a fast-compiling, tightly-integrated
tools suite. Once again, Xilinx executes on this expectation with
ISE 6.3i, setting a new industry standard for quality of results
and productivity," said Rich Sevcik, executive vice president,
Programmable Logic Solutions Group at Xilinx. "ISE delivers
new technology that enables designers to maximize the potential
of our Platform FPGA architectures and fully realize their advantages
over less-innovative ASIC approaches."
Next-Generation Virtex-4 FPGA Design
ISE 6.3i includes a variety of enhancements aimed at increasing
productivity and supporting the 100+ new device features available
with Virtex-4 Platform FPGAs, as detailed in a related announcement
today (http://www.xilinx.com/prs_rls/silicon_vir/0493virtex4.htm).
Virtex-4 design support has been available to Xilinx customers participating
in the Virtex-4 early access program since February of this year.
- ISE architecture wizards enable rapid configuration of high-performance
Virtex-4 silicon features, including the new ChipSync Wizard for
fast and accurate source synchronous interface design, and the
XtremeDSP Slice Wizard driving the new Virtex-4 XtremeDSP. The
Rocket IO Wizard eases serial I/O design up to 11.1 Gbps, and
the Clocking Wizard functionality supports advanced internal FPGA
clock configuration for all Virtex-4, Virtex-II Pro and Spartan-3
family devices.
- PACE (ISE pin and area constraints editor) support for Virtex-4
delivers advanced pin management and logic area floorplanning
in a fast and easy-to-use graphical interface. PACE includes critical
engineering rule checks for Simultaneous Switching Outputs to
help identify potential ground bounce problems.
- The Xilinx Synthesis Tool (XST) delivers improved performance
and better utilization over previous releases, in addition to
support for the new Virtex-4 device features.
- The PlanAhead Hierarchical Floorplanner (recently acquired with
Hier Design) offers a new integrated option for high-density FPGA
design, supporting the new Virtex-4 devices in addition to Virtex-II
Pro and Spartan-3 FPGAs. PlanAhead enables resolution of density
challenges and high-performance timing closure, as well as design
reuse and IP optimization earlier in the design cycle and at higher
levels of abstraction in order to achieve overall better performance
and faster design completion.
- The optional ChipScope Pro 6.3i real-time hardware debugger
now supports Linux Red Hat Enterprise 3.0, offers a 60-day evaluation
version, and includes new storage qualification for more efficient
use of trace debug memory.
We have seen a continual improvement in our FPGA designs with
the use of ISE 6 design tools from Xilinx," commented Antonio
Borrego, FPGA design engineer at StorageTek. "ISE 6 has not
only shortened the time required for us to synthesize and implement
our designs, but also makes very efficient use of internal device
features, and allows for easy portability of projects between our
various working groups."
Low-cost Design Platform
ISE 6.3i continues to deliver the industry's fastest push-button
performance on the lowest-cost FPGA platforms. The built-in "timing-driven
mapping" feature merges the placement and mapping phases to
automatically achieve up to 30 percent better performance on highly
utilized designs as compared to designs not leveraging this capability,
making it possible to put more logic into a smaller device without
sacrificing timing goals. The ISE PACE pin-assignment and constraints
editor also supports local clocking for Spartan-3 designs, making
off-chip memory interface design quicker, easier and with fewer
design iterations. These new features enhance the lower density,
lower cost advantages of Spartan-3 devices as ASIC replacements.
In addition, the ISE WebPACK 6.3i solution offers fast, convenient
access to a subset of the ISE Foundation design tools for various
FPGA and CPLD devices. It is a complete development environment
that meets design demands ranging from simple glue logic to medium-density
"system-on-chip" FPGA platforms with unmatched productivity
and performance. The ISE WebPACK provides easy download and installation
to more than 150,000 users worldwide.
Platform, Pricing and Availability
ISE 6.3i supports all leading-edge Xilinx product families including
the three platforms of the Virtex-4 FPGAs, Spartan-3 Series FPGAs,
and CoolRunner-II CPLDs. All versions of ISE software packages support
Windows 2000 and Windows XP. The ISE Foundation, ISE Alliance, and
ISE BaseX configurations also support Linux Red Hat Enterprise 3.0
(with limited support for Linux Red Hat 8.0 and 9.0). ISE Foundation
and ISE Alliance also support Solaris 2.8 and 2.9.
All ISE 6.3i configurations are immediately available with prices
ranging from $695 to $2495 U.S. list. The free, downloadable ISE
WebPACK 6.3i solution (www.xilinx.com/ise/webpack)
is also available and ideally suited for the Xilinx Spartan-3 FPGA
and Cool Runner CPLD products.
New customers can access the ISE Evaluation package at www.xilinx.com/ise_eval
for a 60-day version of ISE Foundation at no charge. A free 60-day
evaluation version of the ChipScope Pro 6.3i hardware debugger for
Windows, Solaris and Linux is also available at www.xilinx.com/chipscope.
About Xilinx
Xilinx is the worldwide leader in complete programmable logic
solutions. For more information, visit www.xilinx.com.
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