FOR IMMEDIATE RELEASE

XILINX ACCELERATES WORLD'S FASTEST FPGAS -
NEW ISE 7.1i RELEASE DELIVERS 70% LOGIC PERFORMANCE ADVANTAGE

Easy to use ISE design tools underscore leadership in every
FPGA performance category

GLOBAL PRESS SUMMIT, MONTEREY, Calif., March 1, 2005 - Xilinx, Inc. (NASDAQ: XLNX) today announced immediate shipment of the 7.1i release of its Integrated Software Environment (ISE) optimized for the Xilinx Virtex -4 and new Spartan -3E FPGA families. ISE 7.1i incorporates unique elements of integration, speed, and ease of use to resolve some of the most pressing challenges for its rapidly growing user base of over 200,000 designers. The new tool integrates key power analysis, hierarchical design, simulation, and debug features, and supports the growing movement to Linux-based design environments. Also included are new speed files for the Virtex-4 family, the world's fastest FPGAs in every performance category. Designers can now leverage a logic fabric performance advantage of up to 70 percent, as well as overwhelming DSP, embedded processing and connectivity performance advantages over competing offerings. Also included in ISE 7.1i is full support for the new Spartan-3E family, the world's lowest cost FPGAs.

"Well-integrated design tools enable high-performance systems designers to leverage the convergence of logic, DSP, embedded processing, and connectivity on a single programmable platform," said Rich Sevcik, executive vice president of the Programmable Solutions Group at Xilinx. "Fast cycle times and ease of use are equally critical for designers of high-volume products who are embracing the time-to-market and flexibility benefits available only with programmable logic. Xilinx invests more than anyone else in the PLD industry to provide best-in-class design tools for both high-performance and high-volume applications."

New Facets of Integration, Speed, and Ease of Use
ISE 7.1i includes new key ease-of-use features to speed engineers through the design flow faster with easily visible implementation results each step of the way. New Design Summary View and Message Filtering features highlight important design information, reducing the need to search through detailed report files. New Technology Viewer displays post-synthesis implementation results in an easy-to-navigate schematic view.

Two new simulators are also incorporated into ISE 7.1i for faster simulation and higher design capacity - ISE Simulator and ModelSim Xilinx Edition-III. Augmenting simulation with real-time in-silicon debug, ChipScope Pro and ISE 7.1i enable real-time verification that requires only half the time of ASIC or competing FPGA verification flows. ChipScope Pro now also allows designers to verify and debug systems remotely from anywhere in the world through a network connection.

ISE 7.1i integrates with the Xilinx PlanAhead option to provide a new layer of hierarchical design and an early analysis feature set that improves system performance and ease of use. Using the PlanAhead tool can boost performance up to 2X and shorten design cycles with incremental compile, fewer timing iterations, and more efficient IP planning and re-use.

ISE 7.1i sets the stage for higher-density design and development, by supporting 64-bit Linux. Importantly, ISE 7.1i plugs directly into existing EDA design flows with deep integration to third-party EDA partner design tools for synthesis, simulation, HDL analysis and verification, to name a few.

"Over the years, Xilinx and Synplicity have worked together to provide FPGA designers with a complete, robust and performance-leading solution for Xilinx FPGAs," said Jeff Garrison, director of marketing at Synplicity. "The tightly integrated ISE 7.1i software design suite and new cost-optimized Spartan-3E FPGA family ultimately enables our customers to achieve their performance goals quickly while minimizing design area, resulting in a smaller device or lower-speed grade requirement. This is a key asset for today's fast-changing end markets."

ISE 7.1i: Performance, Power and Cost
ISE 7.1i leverages the performance features of the Virtex-4 multi-platform FPGA family for logic-intensive, signal processing, high-speed serial connectivity and embedded processing applications. Enabled by the revolutionary Advanced Silicon Modular Block (ASMBL) architecture and advanced 90nm triple-oxide technology, Virtex-4 FPGAs deliver more options, higher performance and lower power than any FPGA family available today. Enabled by the advances in Proactive Timing Closure and new speed file support in ISE 7.1i, Virtex-4 FPGAs reinforce their platform leadership in every performance category, including 1.6x higher LVDS I/O bandwidth, 3x higher memory interface bandwidth, 1.2x higher on-chip RAM speed, 1.4x higher DSP performance with a 32-tap FIR filter example, 3x higher embedded processing performance, and up to 1.7x logic performance advantages over the nearest competing FPGAs.

Xilinx has invested significantly in developing a methodology that fairly and accurately measures logic performance on real customer designs. A good methodology must correctly constrain both the synthesis and place and route tools, evaluate the most important clock in the design (not only the slowest clock), use equivalent switch settings for each tool, and compare similar speed grades for each device. This accurate methodology demonstrates the logic fabric performance advantage for Virtex-4 of up to 70 percent, and on average 14 percent over competing FPGAs.

Engineers are also concerned with power reduction, whether designing the largest wireless base stations or the smallest portable handheld devices. Analysis using the ISE 7.1i XPower tool and the Xilinx Web Power Tools shows how Virtex-4 FPGAs consume as little as 1/10th the power of competing 90nm FPGAs. Aided by these tools, designers can close on their performance targets within their power budget quickly and accurately. ISE 7.1i Xpower analysis also supports Xilinx CoolRunner-II CPLDs, which provide RealDigital technology for the lowest dynamic power consumption of any CPLD family in the industry.

Cost is also a primary challenge for designers. ISE 7.1i enables additional high-volume designs with support for the Spartan-3E FPGA family and ultra low-power Spartan-3L FPGAs. Specifically, Spartan-3E FPGAs are priced at under $2.00*, offering 100K system gates for under $2.00 and 1.2M system gates for under $9.00* - setting a new cost-per-logic standard for low cost FPGAs.

Platform, Pricing and Availability
ISE 7.1i supports all leading-edge Xilinx product families including the three platforms of the Virtex-4 FPGAs, Spartan-3 Generation FPGAs, and CoolRunner-II CPLDs. All versions of ISE software packages support Windows 2000 and Windows XP and Linux Red Hat Enterprise 3.0. ISE Foundation also supports Solaris 2.8 and 2.9. All ISE 7.1i configurations are immediately available with prices ranging from $695 to $2495. The free, downloadable ISE WebPACK 7.1i solution will be available in late March 2005.

New customers can access the ISE Evaluation package at www.xilinx.com/ise_eval for a 60-day version of ISE Foundation at no charge. A free 60-day evaluation version of the ChipScope Pro 7.1i hardware debugger for Windows and Linux is also available at www.xilinx.com/chipscope.

# 0530
*500K unit volume, second half 2006

Editorial contact:

Paula Larson

Xilinx Public Relations

(408) 879-6802

paula.larson@xilinx.com