FOR IMMEDIATE RELEASE

XILINX IMPROVES PERFORMANCE AND PRODUCTIVITY
FOR VIRTEX-4 PLATFORM FPGA DESIGNS WITH PLANAHEAD 7.1 TOOL

New tool delivers an additional 15% performance improvement and up to 50% faster design closure

SAN JOSE, Calif., May 23, 2005 - Xilinx, Inc. (NASDAQ:XLNX) today announced the immediate availability of its next generation PlanAheadTM 7.1 FPGA design and analysis tool. The tool enables designers to boost logic performance by 15%, and in some cases boost performance by 2X, for Xilinx high-density FPGA designs. This performance boost can save designers an entire speed grade, resulting in significant overall cost savings. Additionally, the PlanAhead tool includes a host of new features to help users achieve up to 50% faster timing closure to meet even the most aggressive design goals.

PlanAhead is employed between synthesis and place & route, enabling designers to rapidly analyze, modify and achieve superior performance on each of the individual design blocks. Blocks can then be stitched together in a final assembly phase. The tool's hierarchical design methodology further extends the incremental design capabilities available in Xilinx's ISE software suite and has no parallel in the FPGA design tools domain.

"We've been using the PlanAhead tool for a year and a half and due to its excellent analysis and implementation capabilities now include the tool in our default design and prototyping flow," said Fernando Martinez of NVIDIA. "We're extremely impressed with the unique capabilities of the tool which help us meet our performance goals in the shortest possible time."

"Over the last two years, we have used the PlanAhead tool extensively to achieve faster timing closure," said Jahan Lotfi, design engineer at Cortina Systems. "By using this innovative product along with excellent support from the Xilinx PlanAhead team, we've consistently achieved fast timing closure which is critical in our fast paced environment."

High-density Performance Advantage & Faster Timing Closure
PlanAhead 7.1 provides dramatic performance improvements to designs targeting the Virtex-4 Platform FPGA family - already the industry's fastest FPGAs with up to 70% higher logic performance over competing solutions. These improvements can save designers a full speed-grade. Additionally, designers can leverage new analysis and design visualization features to identify and resolve design problems quickly. Achieving design closure in half the time results in the savings of valuable design time and a reduction in overall design cost compared to traditional design methodologies. The tool's unique use of a hierarchical design methodology enables a block-based incremental solution to reduce implementation runtimes and provide consistent results. The tool also includes the following new features to help achieve faster timing closure:

• Metric Maps: Metric Maps offer a visual display of the key success metrics for a design. Metric Maps help detect problems such as routing congestion and timing bottlenecks offering users an earlier opportunity to address problems in the floor plan and improve design performance.
• Gate-level Floor planning: This new capability provides more control and insight at the logic-gate level, allowing users to lock logic to specific sites for better performance and ensured use of high-speed routing channels.
  
• Intuitive User Interface: A new tabbed window environment eliminates overlapping windows and presents design information in a more concise and easy to understand way. Users can customize the look and feel of the software by saving layouts for future use.
  
• Improved Accuracy of Timing Analysis: TimeAhead Timing Analysis now includes the use of speed files along with improvements to the timing results environment, allowing greater visibility into the performance of the design.
  

Platform, Pricing, and Availability
The PlanAhead 7.1 tool supports all leading-edge Xilinx FPGA families, including the Virtex-4 Platform FPGA Family and Spartan-3 Generation Family. The tool supports Windows 2000 and Windows XP, Red Hat Enterprise Linux 3, and Solaris 2.8 and 2.9. PlanAhead 7.1 is immediately available for use with the Xilinx Integrated Software Environment (ISE) 7.1i FPGA design suite. The PlanAhead 7.1 tool is being offered at a promotional price of $5,995. Included in this price is training on the 7.1 release. For more information about the PlanAhead tool, contact a Xilinx sales office or visit: http://www.xilinx.com/planahead.

Services & Support
Xilinx also provides complete support for the PlanAhead tool, including online technical support, a two-day training course called "Designing with PlanAhead", and a bundled service offering called "PlanAhead QuickStart!" The "PlanAhead QuickStart!" package includes an applications engineer at the customer site for one week to provide consultation on architecture optimization, design environment configuration, and the "Designing with PlanAhead" training course.

About Xilinx ISE 7.1i Software
ISE 7.1i continues to deliver the fastest performance available in FPGA design, up to 70% faster than the nearest competing solution. ISE provides programmable logic designers with an intuitive, front-to-back design environment for all leading Xilinx device families. ISE delivers logic design solutions to over 200,000 FPGA and CPLD users worldwide. ISE 7.1i supports all leading-edge Xilinx product families including the three platforms of the Virtex-4 FPGAs, Spartan-3 Generation FPGAs, and CoolRunner-II CPLDs. All versions of ISE software packages support Windows 2000 and Windows XP and Linux Red Hat Enterprise 3.0. ISE Foundation also supports Solaris 2.8 and 2.9. For more information about the ISE 7.1i software suite, visit www.xilinx.com/ISE.

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