FOR IMMEDIATE RELEASE

XILINX TO PARTICIPATE IN THE OIF COMMON ELECTRICAL INTERFACE INTEROPERABILITY TESTING AT DesignCON WEST 2005

Xilinx to Showcase its Virtex-II Pro Series FPGAs
Driving Chips, Backplanes and Cables at Rates of Up to 10.3125 Gbps at Booth #224

January 25, 2005

What: DesignCon 2005 (http://www.xilinx.com/events/tradeshows/designcon05/index.htm)
When: January 31-February 3, 2005
Where: Santa Clara Convention Center, Santa Clara, Calif., Xilinx Booth #224

Optical Internetworking Forum's Common Electrical Interface Interoperability Testing
Xilinx will participate in the Optical Internetworking Forum's (www.oiforum.com) Common Electrical Interface (CEI) interoperability demonstration in Booth #647, featuring the latest advances in CEI technology. Xilinx will participate in interoperability testing for 6G short reach, 6G long reach, 11G short reach and 11G long reach interfaces. The live demonstrations will showcase how the recently approved CEI IA and continuing CEI work in progress can interoperate across multiple vendors' transmitters, backplanes and receivers.

Highlights of Xilinx Demonstrations (Booth #224)

• High-speed data transfer of over 10Gigabaud per lane and up to 6 lanes of traffic using Aurora Open Protocol
  
  
• Virtex-II Pro X driving 10Gbps over industry standard ATCA backplane built by Kaparel
  
  
• Virtex-II Pro driving an industry standard 5 slot ATCA chassis to demonstrate 1x Advanced Switching protocol, MultiBERT error testing reference design and Mesh Fabric reference design

Xilinx-related Panel & Track Activities
IEC Executive Panel: "What is Design for Yield and How Do we get there?"
February 3, 3:45-5:00 p.m.
Vincent Tong, vice president, Operations, Xilinx, and other industry experts will debate the issues in getting the design side and the manufacturing side to cooperate for greater yield at smaller geometries. Moderator: Gabe Morretti, technical editor, ASIC & EDA, EDN Magazine.

Other Panel & Track Activities -

• Signal Integrity Technology for High Speed Serial Link Design, January 31, 1:30-4:30 a.m., Dr. Howard Johnson
  
  
• Edge-Optimized Equalization Extends Performance in Multi-Gigabit Serial Signaling, February 2, 9:40-10:30 a.m., Brian Brunn, Senior Staff IC Design engineer, Xilinx, Inc.
  
  
• Beyond 10Gbps Next-Generation Serial Interfaces, February 2, 2:00-2:40 p.m., Thomas Palkert, system architect, Xilinx, Inc.

Partner Activities
Several partners will showcase demonstrations featuring the Virtex-II Pro and Virtex-II Pro X FPGAs including Ansoft (Booth #217), FCI (Booth #521), Mentor Graphics (Booth #633), Meritec (Booth #727), Molex (Booth #200), Northrup Grumman (Booth #XXX), Teradyne (Booth #211) and Tyco Electronics (Booth #731).

About the Xilinx High-Speed Serial Initiative
The Xilinx High-Speed Serial Initiative was established to accelerate the industry's migration from parallel to high-speed serial I/O by delivering a new generation of connectivity solutions for system designers. The trend toward high-speed serial connectivity is being driven by companies across a wide range of industries as a means to reduce system costs, simplify system design, and provide scalability to keep pace with current and future bandwidth requirements. Serial solutions will ultimately be deployed in nearly every aspect of every electronic product imaginable, from chip-to-chip interfacing, backplane connectivity, and box-to-box communications. For more information please see http://www.xilinx.com/serialsolution.

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