DSP: Designing for Optimal Results

High-Performance DSP Using Virtex-4 FPGAs

Chapter 1

• Digital Signal Processing Design Challenges
  Our insatiable hunger for electronic gadgets that provide high-quality audio, video, data or all three, is spiraling up the processing power that is needed to process these signals. Digital signal processing (DSP) systems, within both infrastructure and customer premise equipment must provide increasing levels of performance and flexibility to handle the new requirements yet provide greater scalability for achieving higher economies of scale.

Chapter 2

• XtremeDSP Design Considerations
  This chapter provides technical details for the XtremeDSP Digital Signal Processing (DSP) element, the DSP48 slice.

  The DSP48 slice is a new element in the Xilinx development model referred to as “Application Specific Modular Blocks” (ASMBL). The purpose of this model is to deliver off-the-shelf programmable devices with the best mix of logic, memory, I/O, processors, clock management, and digital signal processing. ASMBL is an efficient FPGA development model for delivering off-the-shelf, flexible solutions ideally suited to different application domains.

Chapter 3

• DSP48 Slice Math Functions
  The DSP48 slice efficiently performs a wide range of basic math functions, including adders, subtracters, accumulators, MACs, multiply multiplexers, counters, dividers, square-root functions, and shifters. The optional pipeline stage within the DSP48 tile ensures high performance arithmetic functions. The DSP48 column structure and associated routing provides fast routing between DSP48 tiles with less routing congestion to the FPGA fabric. This chapter describes how to use the DSP48 slice to perform some basic arithmetic functions.

Chapter 4

• MAC FIR Filters
  This chapter describes the implementation of a Multiply-Accumulate (MAC) Finite Impulse Response
  (FIR) filter using the DSP48 slice in a Virtex-4 device. Because the Virtex-4 architecture is flexible,
  constructing FIR filters for specific application requirements is practical. Creating optimized filter
  structures of a sequential nature saves resources and potential clock cycles.

  This chapter also demonstrates two sequential filter architectures: the single-multiplier and the dual multiplier MAC FIR filter. Reference design files are available for the System Generator in DSP,
  VHDL, and Verilog. These reference designs permit filter parameter changes including coefficients
  and the number of taps.

Chapter 5

• Parallel FIR Filters
  This chapter describes the implementation of high-performance, parallel, full-precision FIR filters
  using the DSP48 slice in a Virtex-4 device. Because the Virtex-4 architecture is flexible, it is practical
  to construct custom FIR filters to meet the requirements of a specific application. Creating optimized,
  parallel filters saves either resources and potential clock cycles.

  This chapter also demonstrates two parallel filter architectures: the Transposed and Systolic Parallel
  FIR filters. The reference design files in VHDL and Verilog permit filter parameter changes including
  coefficients and the number of taps.

Chapter 6

• Semi-Parallel FIR Filters
  This chapter describes the implementation of semi-parallel or hardware-folded, full-precision FIR filters using the Virtex-4 DSP48 slice. Because the Virtex-4 architecture is flexible, constructing FIR filters for specific application requirements is practical. Creating optimum filter structures of a semi-parallel nature saves resources and potential clock cycles. Therefore, optimum filter structures of a semi-parallel nature can be created without draining resources or clock cycles.

  This chapter also demonstrates two semi-parallel filter architectures: the four- multiplier FIR filter using distributed RAM and the three-multiplier FIR filter using block RAM. These filters illustrate how resources are saved by using available clock cycles and hardware-folding techniques. Reference design files are available for system generator in DSP, VHDL, and Verilog. The reference designs permit filter parameter changes including coefficients and the number of taps.

Chapter 7

• Multi-Channel FIR Filters
  This chapter illustrates the use of the advanced Virtex-4 DSP features when implementing a widely used DSP function known as multi-channel FIR filtering. Multi-channel filters are used to filter multiple input sample streams in a variety of applications, including communications and multimedia.