I/O Magazine

Connectivity Solutions for Programmable Logic Professionals
Issue 2 : Making Sense of the Complex

Welcome

• Making Sense of the Complex
  Editorial by Abhijit Athavale, Sr. Marketing Manager, Connectivity Solutions.

Articles

• A Paradigm Shift in Signal Integrity and Timing Analysis
  Emerging high-speed interfaces are breaking traditional analysis approaches, forcing a paradigm shift in analysis tools and methodology.
• Capturing Data from Gigasample Analog-to-Digital Converters
  Interfacing National Semiconductor’s ADC08D1500 to the Virtex™-4 FPGA allows quick-start customer application development.
• Xilinx/Micron Partner to Provide High-Speed Memory Interfaces
  Micron’s RLDRAM II and DDR/DDR2 memory combines performance-critical features to provide both flexibility and simplicity for Virtex-4-supported applications.
• Implementing High-Performance Memory Interfaces With Virtex-4 FPGAs
  You can center-align clock-to-read data at “run time” with ChipSync technology. You can center-align clock-to-read data at “run time” with ChipSync™ technology.
• Debugging and Validating PCI Express I/O
  With these tips and tricks for using a logic analyzer, you can speed time to market and increase confidence in your design.
• Using Complex Triggers in the Identify Debugger
  You can obtain huge productivity gains with Synplicity’s powerful and comprehensive FPGA debug tool.
• Understanding the PCI-SIG Compliance Program
  This program is the key to the successful launch of any product that incorporates PCI-SIG technologies such as PCI, PCI-X, or PCI Express.
• Successful DDR2 Design
  Mentor Graphics highlights design issues and solutions for DDR2, the latest trend in memory design.
• Board Design Panacea
  The 7Circuits tool algorithmically solves FPGA pinout problems and synthesizes PC board schematics.
• Deliver Efficient SPI-4.2 Solutions with Virtex-4 FPGAs
  Virtex-4 devices offer an ideal platform for source-synchronous designs like the widely adopted SPI-4.2 interface.
• A Low-Cost PCI Express Solution
  Spartan™ FPGAs are ideal for next-generation PCI applications and systems.
• How to Detect Potential Memory Problems Early in FPGA Designs
  System compatibility testing for FPGA memory requires methods other than traditional signal integrity analysis.
• Taking Rugged I/O Cabling and Connectors to Higher Speeds
  You now have the option to take copper cabling and connectors to 12.8 Gbps and beyond.
• New PCI Express Solution Simplifies Video Security Applications
  How to implement a video security system using PCI Express.
• Designing a Spartan-3 FPGA DDR Memory Interface
  Xilinx provides many tools to implement customized DDR memory interfaces.

Product Reference

• 10-Gigabit Ethernet MAC v7.0
  The LogiCORE™ 10-Gigabit Ethernet MAC core is a single-speed full-duplex 10 Gbps Ethernet Media Access Controller (MAC) solution that enables the design of high-speed Ethernet systems and subsystems.
• Tri-Mode Ethernet MAC v2.2
  The LogiCORE Tri-Mode Ethernet Media Access Controller (TEMAC) core supports half-duplex and full-duplex operation at 10 Mbps, 100 Mbps, and 1 Gbps.
• Virtex-4 Embedded Tri-Mode Ethernet MAC Wrapper v4.1
  The LogiCORE Virtex-4 Embedded Tri-mode Ethernet Media Access Controller (MAC) Wrapper automates the generation of HDL wrapper files for the Embedded Tri-Mode Ethernet MAC in Virtex-4 FX devices using the CORE Generator tool.
• XAUI v6.1
  The Xilinx LogiCORE XAUI core is a high-performance, low pin count 10 Gbps interface intended to allow physical separation between data-link layer and physical layer devices in a 10-Gigabit Ethernet system.
• Memory Interfaces Reference Design
  Give your designs the Virtex-4 FPGA advantage.
• Interfacing QDR ll SRAM with Virtex-4 FPGAs
  QDR II SRAM devices provide a suitable solution for memory requirements when partnered with Virtex-4 FPGAs.
• Xilinx PCI Express Solution
  PCI Express has emerged as the next generation technology replacing PCI. It provides higher performance and increased bandwidth while maintaining the flexibility and familiarity of PCI.
• Spartan-3 Generation IP
  Optimized for the World’s Lowest-Cost FPGAs.

Education

• Signal Integrity for High-Speed Memory and Processor I/O
  Learn how signal integrity techniques are applicable to high-speed interfaces between Xilinx FPGAs and semiconductor memories. This course teaches you about high-speed bus and clock design, including transmission line termination, loading, and jitter.
• PCI Express Design Flow
  By learning PCI Express core protocol fundamentals, designers will gain a working knowledge of how PCI Express can be used in their systems. This course focuses on PCI Express protocol subjects that designers using the Xilinx PCI Express should understand in order to complete their designs faster and easier.
• Designing with Multi-Gigabit Serial I/O
  Learn how to employ RocketIO™ MGT serial transceivers in your Virtex-II Pro design. Understand and utilize the features of the RocketIO transceiver blocks, such as CRC, 8b/10b encoding, channel bonding, clock correction, and comma detection.