Use CoreFire, the FPGA Design Enabler, for quick and easy high-performance DSP application development with Xilinx Virtex-II FPGAs and Annapolis Micro Systems’ COTS hardware.

DSP developers and their customers know FPGA-based processing outperforms conventional processors on a board-for-board comparison, resulting in significant improvements in processing speed, size, weight, power, and costs. Your FPGA design can be a customized parallel processing chip, specifically crafted for a particular application, accelerating the application to run in hardware and at hardware speeds far faster than could be achieved with software on a generic processor.

• Process data in real time, on site, saving all the time and money involved in data collection and off-site processing.
• Modify the processing by simply reconfiguring the chip (by download-ing a different FPGA file) to fix bugs, to adapt to a new set of interface requirements, or to modify the processing in response to application input data or processed results.
• Deliver new applications in place, with no human on-site intervention, by any means of file transfer, including Internet, internal network, hard drive storage, smart card, or wireless modem.

You need a quick and easy way to develop, modify, and test your applications. With VHDL, Verilog, or schematics, even the most experienced ASIC designers need many months to develop applications using upwards of 40 million gates for a single VME or PCI slot.

You can jumpstart your DSP design process – saving time and money – by using the eighth-generation, commercial off-the-shelf (COTS), general purpose Xilinx Virtex™-II FPGA-based hardware from Annapolis Micro Systems, Inc.

You can develop at the application level with the easy-to-learn CoreFire™ FPGA Design Enabler. It’s loaded with high-performance IP modules, created for your use by FPGA application design experts.

Meet the Demand for Real-Time DSP Applications

Managing digital signal processing data in real time for applications like radar and image processing is very demanding. You need:

• High-speed real-time processing
• Very fast data rates
• A combination of complex and real data types
• Integer and floating point data repre-sentations and computation
• Variable and changing data path sizes

• Chip performance in excess of 300 MHz
• Multiple on-chip memory banks for vector-based processing
• High ratio of memory to logic
• Fast embedded multipliers
• 16 pre-engineered clock domains to support the multiple frequencies and multiple-phase requirements of complex system design.

The data comes into the system at 1200 MegaSamples/second with 8 bits per sample. This stream is broken into 16 data streams and processed with polyphase FIR filters and FFTs. The resulting data is again split into 16 channels, the nine most interesting of which are chosen for further processing. Channels 1-3 are sent into the first radar signal processing module, 4-6 are sent into the second radar signal processing module, and 7-9 are sent into the third radar signal processing module, all at 300 MB/s per channel.

The pre-channelizer raw data, at 1200 MB/s, is divided into three streams of 400 MB/s each. Each stream is stored in its own SDRAM block. The appropriate raw data is folded back into the radar signal processing with the channelizer-processed data. The radar signal processors perform filters, FFTs, and other DSP functions on the data.The final result is sent to buffer memory, and then out to disk at 600 MB/s.

Use COTS Hardware from Annapolis for Fast Deployment

On the right side of Figure 2 is the Annapolis WILDSTAR™ II VME board. This board is available with one, two, or three Virtex-II 6000 or 8000 FPGAs, with up to 72 MB of DDR2 SRAM in 18 banks, up to 384 MB of DDR SDRAM in three banks, and programmable flash memory for storing FPGA files for fast reconfiguration.

On the top left side of Figure 2 is the Annapolis 1.5 GHz A/D I/O card, which, for this application, plugs into the top slot of the WILDSTAR II card. This board comes with a MAX 104 or MAX 108 8-bit A/D converter, one Virtex-II 1000 or 3000, one Virtex-E 1000 or 2000, with up to 2 MB of DDR2 SRAM accessible by the Virtex-II bridge PE and up to 16 MB of ZBT SRAM in four banks accessible by the Virtex-E PE.

On the bottom left side of Figure 2 is the Annapolis Fibre Channel 2 I/O card, which, for this application, plugs into the bottom slot of the WILDSTAR II card. This board has four full duplex Fibre Channel 2 I/O channels, with peak rates of 200 MB each way per channel. The board comes with two QLogic ISP2312s, a Virtex-II 4000, 264 MB of DDR SDRAM in four banks, and an IBM PowerPC™ 405 running Linux.

Figure 3 shows the boards connected together and ready to fit into one slot in the VME chassis. The ADC on the 1.5 GHz A/D I/O card performs the analog input and A/D conversion. The Virtex-II and Virtex-E FPGAs on the 1.5 GHz A/D I/O card create parallel data streams and per-form the channelizer function, using polyphase filters, FFTs, and other DSP functions, as well as data reduction.

The channelized data and raw data are both split into three paths in the Virtex-II PE0 on the WILDSTAR II card. Each Virtex-II PE on the WILDSTAR performs radar signal processing functions. The Virtex-II PE1 on the WILDSTAR II card gathers and processes the results for output to the Fibre Channel 2 I/O card.

The Virtex-II FPGA on the Fibre Channel 2 I/O card accepts the data from the WILDSTAR II card, buffers it, and sends it out to disk via the four Fibre Channel 2 channels with the help of the QLogic and PowerPC chips.

Table 1 is a comparison of the system data transfer speeds provided by this Annapolis system to the data transfer speeds required by this channelizer application. You can see that the system easily meets the throughput requirements for the channelizer application.

Table 1 - System data transfer speeds versus channelizer requirements

These WILDSTAR II and I/O boards are the eighth-generation of Xilinx FPGA-based, high-performance process-ing boards produced by Annapolis Micro Systems. Annapolis continues to push the high-performance envelope, using latest-standard Xilinx FPGAs.

You Can Build Your Application Quickly and Easily with CoreFire

You can see that the channelizer application fits on the chosen WILDSTAR II system, so acquiring readily available hardware for your application will be easy. The next step is to figure out how you will develop the host software and FPGA implementations for your application. Remember, this project stretches across three different printed circuit cards and six different FPGAs.

The classic VHDL methodology for implementing applications on FPGAs is difficult, and requires expert knowledge and countless months of painstaking work. You cannot wait months to deploy your product. You need a tool that will allow you to deploy your project within weeks, not months or years. You must be able to develop new application files rapidly and easily, as well as accommodate specification changes, functional additions, and algorithm development.

Using the CoreFire FPGA Design Suite from Annapolis, you can implement each of your algorithms in as little as a few hours. Use the standard WILDSTAR II C or Java API to write your host program. The CoreFire board support packages handle all the I/O, memory, and FPGA interfaces seamlessly, providing excellent performance. Refer to the CoreFire screen display in Figure 4.

CoreFire is a graphical user interface FPGA application development tool that allows you to build your application very quickly by dragging and dropping library elements onto the design window. Choose from more than 400 expertly crafted mod-ules. Modify your input and output types, numbers of bits, and other variables by changing module parameters with pull-down menus. Move modules around on the screen and reconnect with a flick of the mouse.

The modules automatically provide cor-rect timing and clock control. Insert debug modules to report actual hardware values for in-the-loop debugging. Hit the Build Button to check for errors and sizes and to build an encrypted EDIF file. Use the Xilinx ISE tool to place-and-route each FPGA design.

Modify and use the jar file created by the CoreFire build to load your new file into your WILDSTAR II and I/O card hardware. Use the CoreFire debugger to view and modify register and memory contents in the FPGA, and to step through the data flow of your design running in the real physical hardware.

Armed with your debug results, you will find it very easy to use the CoreFire design window to modify and rebuild your FPGA design until you are satisfied with the results. Use the CoreFire program to build and debug each of your FPGA designs, and then use the jar file and the WILDSTAR II API to develop your overall host program.

Conclusion

It is easy to push the DSP performance limits with Virtex-II FPGAs and Annapolis Micro Systems boards. Some of our customers have gone from initial inquiry to first deployment in as short a time as two months.

When you buy high-performance, worldclass, Virtex-II-based off-the-shelf hardware from Annapolis, it is easy to build and modify applications. You have more time to fine-tune your algorithms. You can get prototypes up and running sooner, so you have more time to test market your product.

Final development is just as easy. You will be in the market far ahead of your competition, saving time and money. To learn more, contact Annapolis Micro Systems, Inc., at 410-841-2514, or visit our website at www. annapmicro.com.

Printable PDF version of this article.  (02/15/03) 270 KB