Siemens has developed a powerful diagnostic tool for its high-volume telephone switches. Advanced FPGA technology and high-productivity EDA tools from Xilinx have enabled sophisticated test strategies.

Most people are unaware that hundreds of microprocessors are involved in placing a cellular telephone call. Although this may be a surprising fact for the average cell phone user, mobile communications experts are even more astonished that such a complex system is stable and seemingly robust.

For despite a well-defined development methodology and quality assurance measures, bugs are sure to exist in any microprocessor code or software. Particularly annoying are sporadic bugs, which show up only under special, rare circumstances at intervals as long as months apart. Typically, such bugs are associated with the dynamics of the multiprocessor system.

Of course, there are plenty of debug tools to analyze software, but applying them may change the dynamics of the system and can therefore mask the problem. This is where the Siemens Hardware (HW) Tracer comes into its own in identifying software bugs before they can cause problems in the field. Based on Xilinx Virtex™-E FPGAs, HW-Tracer is a standalone, rack-based data capture, analysis, and debug tool.

Hardware Tracer

The HW-Tracer’s task is to acquire, filter, and qualify all bus cycles and additional monitor signals. These signals can be accessed via interfaces on the front panels of every processor and memory board and are recorded in trace memory together with a timestamp that is 2 million cycles deep. The tracer can log the complete activity of the system in real time without interfering with its operation. Moreover, it can also trigger specific events due to a tight coupling with the Coordination Processor’s (CP) operating system.

HW-Tracer is essentially a logic analyzer with many proprietary extensions. Because of the number, high speed, and complexity of these extensions, we developed the HW-Tracer as an in-house tool for Siemens. For example, it tracked processes (whose addresses were determined at runtime) and compiled a view containing only program jumps. To meet the demanding requirements of the new CP generation, HW-Tracer has to cope with a peak data rate of 2 gigabytes per second. Actual cycle rates can even be higher, as data bursts are transferred in a compressed format.

To use the HW-Tracer’s two channels independently for processor or memory, we dynamically reconfigured the FPGA that acts as the heart of the tool. Reconfiguring the hardware to complete two different trace tasks halved the cost of the hardware.

The Technical Challenge

A number of key design considerations decided the final hardware implementation. Because of their reprogrammability and dynamic reconfigurability, we selected Virtex-E FPGAs.

The tasks the HW-Tracer had to perform included:

• Analyze nearly 200 input signals at a system speed of 75 MHz
• Capture a high number of 32-bit buses with a data path as wide as 144 bits, which would stress routing resources
• Cope with signal integrity issues on the board level.

We conducted a feasibility study before we developed the new HW-Tracer. Specifically, we investigated whether FPGA technology was capable of dealing with the necessary system performance. Our study showed that the Xilinx Virtex-E family of FPGAs was the only technology available that could meet the requirements. We chose Virtex-E FPGAs because:

• Virtex-E devices have up to 804 user I/Os and a 130 MHz internal performance level.
• There were more than enough routing resources to capture the 32-bit busses with widths as wide as 144 bits. With densities ranging from 58K to 4M system gates, a cascade chain for wide-input functions, and dedicated carry logic for high-speed arithmetic functions, the Virtex-E FPGAs were ideal for this task.
• The programmable SelectIO™ standards on Virtex-E devices were able to handle signal integrity issues at the board level, supporting 20 high-performance interface standards with as many as 804 single-ended I/Os or 344 differential I/O pairs.
• The fast, high-density, 1.8V Virtex-E family is designed for low-power operation.

The state machines required to control the operation modes of the HW-Tracer could not be pipelined and threatened to limit the achievable system speed. We have found, however, that arithmetic performance is not the bottleneck in today’s leading-edge FPGAs.

Choosing the Design Flow

Despite the extreme performance needed, we decided to code the design in VHDL, which is technology-independent at a high level and controls the implementation via just the constraints in the synthesis and place-and-route tools. We have successfully used this automated design flow already in the past for several FPGA designs. It prevents design issues and saves time when modifying the design.

Only the memory modules had to be instantiated; using the Xilinx CORE Generator™ tool, this proved to be quick and easy to implement.

It was clear that we would have to utilize simulation as if we were developing an ASIC. Simulation (including a gate-level simulation with the VHDL output of Xilinx Alliance Series™ software) added to the overall design time but paid off at the end, when the FPGA was delivered with only two very minor bugs detected.

Striving for Timing Closure

We selected Mentor Graphics’ Leonardo Spectrum™ software to synthesize the design and Alliance Series software for the back-end task. Both tools enabled us to implement a completely automated design flow. This was important because in past designs, timing closure could not be guaranteed; code changes tended to result in new worst-case paths that violated the tight timing constraints. We have experienced this timing constraints problem when designing with ASICs.

The most recent releases of the Leonardo Spectrum synthesis tool address this issue successfully by interacting with Xilinx Alliance software, and thus, reducing the number of design iterations. We have seen improvements on the critical paths as high as 15%.

We carried out many implementation runs to incrementally move toward our performance goal. In our project, we started the development based on preliminary timing data; later updates of the timing data entailed some refinements of the constraints.

We benefited a great deal from the stability and performance of Xilinx design software. We achieved turnaround times of three to four hours for the whole implementation task, which is excellent when taking into account the complexity and tough timing constraints.

Management Views
The CP’s bring-up-phase depended heavily on the availability of HW-Tracer, which was developed in parallel. To address this risk, we added several additional verification steps to the process.

The test equipment included in the VHDL system simulation comprised:

• Two main memory units, each with a million-gate ASIC containing two embedded CPU-cores
• Several different processing units, each with a million-gate ASIC and two CPUs
• Up to 16 peripheral models and an ATM-controller.

“The verification of the HW-Tracer at the virtual, simulated level ensured that it could be immediately used for testing the physical prototype of the CP unit. This is a great advantage over ASIC designs. Using FPGA simulation tools shortened our design time greatly,” said Johann Notbauer, Siemens CES Design Services’ technical director for ASIC and FPGA design. Friedrich Wilhelm, technical director and specialist for proprietary test tools at Siemens, added, “The high logic densities, flexible high-performance interface standards, and pipelining capabilities of Virtex-E combined with the powerful design tools made the choice of FPGA easy.”

Emulation

The application software of the HW-Tracer had to be thoroughly verified before its first use. In this environment, the Tracer design was stimulated by a pattern generator, which was included into the FPGA design using internal Virtex-E block memories. The patterns were again derived from the system simulation. In the final product the pattern generator is used for a “learn mode,” which helps users familiarize themselves with HW-Tracer before being connected to an actual CP unit for test and debug.

Internet Reconfigurable

In order to facilitate troubleshooting on any of the switches installed throughout the world, the HW-Tracer was designed as a portable device and squeezed into a 3U-CompactPCI chassis.

The FPGAs were loaded by the embedded PC, which took the configuration data from the hard disk. Embedded software as well as FPGA design files are accessible on a dedicated homepage – where future updates and upgrades can be downloaded.

Conclusion

The powerful combination of Mentor Graphics’ Leonardo Spectrum synthesis with Alliance software and Virtex-E hardware from Xilinx enabled Siemens to bring its new range of telephone switches to market. Virtex-E FPGAs were used at the heart of the HW-Tracer, which was used to debug and test the Coordination Processor project. The software combination allowed FPGA design iterations to be completed quickly without affecting the tight timing constraints. We chose Virtex-E devices for their high logic densities, high system speeds, flexible system I/O, and ability to perform fast pipelining utilizing the SRL16 mode.

As one customer put it, “The HW-Tracer is the most important debug tool in the CP project.”

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