Xilinx industry-leading design tools provide a low-cost, low-risk, and high-performance logic solution.

Reducing project costs isn’t new to most designers, but in tight economic times the pressure to bring project costs down becomes much more important. In his Xcell Journal Winter 2002 article titled, “When Total Cost Management Counts, Xilinx PLDs Pay Off ” (www.xilinx.com/publications/products/cool2/xc_tcm43.htm), Eric Thacker described how programmable logic devices (PLDs) offer significant benefits in dynamic, rapidly changing markets.

With our ISE development systems and development options, Xilinx not only supports the benefits of PLDs but also offers additional cost savings. ISE 5.2i, the latest release of our design software, delivers a number of productivity technologies that shorten logic design flow, optimize design results, shorten implementation and verification cycles, and provide interactive design assistance. At the same time, ISE 5.2i enables you to realize even faster design performance. The end result to you is cost savings across your entire project.

The shorter design cycles and time-to-market advantages of FPGAs and CPLDs mean that you need less engineering resources. This allows you to make the best use of your staff when difficult economic conditions restrict your ability to hire more engineers. Our fast, efficient, and highly productive ISE software tools help you get the job done in less time, and they make each engineer more productive.

Free ISE WebPACK

The ISE WebPACK™ design suite is the ideal Web-downloadable desktop solution. It offers a complete development environment with modules from ABEL and HDL synthesis to device fitting and JTAG programming. ISE WebPACK tools are a subset of our award-winning ISE Foundation™ design tools, providing instant access to the ISE tools at no cost. By providing a design solution that is always up-to-date, with error-free downloading and single file installation, Xilinx has created a solution that allows instant productivity. Because ISE WebPACK development tools are available for download from the Xilinx website at www.xilinx.com/ise/webpack5, you can get started immediately on designs for leading Xilinx CPLDs and mid-density FPGAs.

This Web-downloadable design solution reduces your design costs by including all the tools you need to complete your design.

ISE WebPACK includes:

• ModelSim Xilinx Edition (MXE-II) Starter Version
  ModelSim XE is a complete HDL simulation environment that has been optimized for programmable logic design, enabling you to quickly verify source code and functional and timing models of your design.
• HDL Bencher
  Within the ISE WebPACK toolset, the HDL Bencher™ test bench generator automatically imports the current HDL design file and creates an editable stimulus waveform by default.
• StateCAD
  The StateCAD FSM wizard automates the state machine design process. You can specify complex state machines to quickly meet tough product requirements. The state machines can then be automatically translated to an HDL format you can include in your design flow.
• ChipViewer
  ChipViewer is a pre- and post-fit graphical utility to assign or view pin placement and implemented logic for all Xilinx CPLD devices. This removes the risks associated with changes late in the design process.
• XPower
  XPower is a graphical power-analysis tool. Total device power, power per-net, fitted, routed, partially routed, or unrouted designs can be easily analyzed.

Optimized Design Performance and Device Utilization
Xilinx ISE design tools have raised the industry standard for both design performance and device utilization. Through patented implementation algorithms, ISE allows you to achieve the fastest possible design performance. Compared with competitive solutions, designs can achieve better than 15% higher performance.

This performance edge means you can potentially target a lower cost device – leveraging faster performance from the software. Thus, you can hit your timing goals earlier, spending less time in the design flow.

For example, based on benchmark data, you can achieve 20% to 30% better performance in Virtex-II Pro™ designs using ISE than you can get from an offering from the leading competitor. In many cases, you can target your design to a slower speed grade device and still achieve targeted design performance.

ISE also reduces project costs by packing more logic into Virtex™-II devices, letting you fit your design in the smallest possible device. Advanced FPGAs are not solely made of look-up tables and flip-flops anymore. Today’s logic fabrics are best described as “feature rich.” This trend requires sophisticated algorithms in both synthesis and implementation tools, providing optimal performance and logic utilization by leveraging new hardware features.

Xilinx ISE development tools separate unrelated functions and assign them to different clusters (called a slice) on the fabric. This avoids conflicting placement constraint and guarantees optimal performance. As the device gets full, powerful algorithms pack unrelated logic into common clusters. This gradual process ensures that the device is utilized at its best, with minimal impact to design performance.

With competing FPGA solutions development tools, the packing of logic requires a special option. With this option turned on, packing is limited, because an unrelated LUT using its 4-inputs and a flip-flop cannot be merged together in any logic element – and the limited packing comes at a cost to design performance. Virtex-II logic utilization with ISE comes out 15% better than the nearest competitive offering. In the Virtex-II fabric, the LUT and flip-flop can be used independently, without restrictions. In Stratix devices, a LUT can-not be used with its flip-flop in all circum-stances, because one input pin of the LUT is shared with the path that has direct access to the flip-flop. By default, when the flip-flop is not fed by any logic, the LUT in that LE is unavailable to the rest of the design. As a remedy, Quartus II tools provide a register packing option (off by default) to enable the packing of LUTs along with the flip-flop. This still does not allow LUTs using 4-inputs to be packed, because the connectivity restriction is still present. Figure 1 shows LUT to flip-flop connectivity in both Virtex-II and Stratix devices.

Advanced Technology Streamlines the Design Flow

ISE is also packed with advanced software technology designed to accelerate the more time-consuming parts of the design and debug logic flow.

Incremental Design is a technology included in ISE that shortens design re-compile times. By locking performance for areas of the design that don’t need to change, Incremental Design lets you perform re-synthesis and re-place-and-route on only those pieces of the design that have to change. This reduction in time adds up fast in the crucial verification cycle, where debug changes are common.

The Xilinx ChipScope™ Pro integrated logic analyzer also delivers added productiv-ity to the verification cycle. Through small, easy-to-place software debug cores, the ChipScope Pro tool allows you to monitor – in real time – any signal in the FPGA. This includes the IBM PowerPC™ 405 peripheral bus in the advanced Virtex-II Pro FPGA. Design signals are captured and brought to the outside world through the FPGA JTAG programming port. This minimizes the amount of dedicated FPGA space and I/O pins required – as opposed to using more traditional ASIC and competing FPGA debug methodologies.

Additionally, signal monitor points can be changed through the ISE FPGA editor without having to re-compile the design, saving even more debug time. The ChipScope Pro analyzer cuts verification times dramatically, even when the device is on the board – or in the field.

Conclusion

For logic design, the true cost of the project includes much more than just device cost. Factors like development cost, project timelines, access to development tools, designer efficiency, ability to achieve device performance goals, and verification costs can have a big impact on the overall project cost.

Xilinx allows you to meet – or beat – your project budget through free ISE WebPACK development tools, other ISE configurations, a complete design environment, ISE’s powerful implementation tools, robust verification technology, and more. As you evaluate various logic design solutions, look at the total costs associated with design tools and designer resources in addition to the cost of the device.

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