The Xilinx Serial Tsunami Initiative is a comprehensive set of programmable serial I/O solutions and system strategies that will help you simplify designs, increase performance, and lower system costs.

Remember the days when serial I/O brought either USB or IEEE 1394 to mind? Not any more. A veritable tsunami of new and evolving serial I/O standards is washing over the technological landscape, delivering promises of higher performance, lower costs, and simpler designs. Remarkable advances in semiconductor technology and the availability of low-power CMOS serial transceivers are driving a migration of tidal wave proportions from parallel to serial interfaces.

Xilinx is at the forefront of this movement. We have been shipping our flagship Virtex-II Pro™ FPGAs (www.xilinx.com/ virtex2pro) since the beginning of 2002. The Virtex-II Pro devices are the only Platform FPGAs with embedded 3.125 Gbps RocketIO™ CMOS serial transceivers. Designing cutting edge serial I/O technologies is a challenging endeavor, but using serial I/Os to build your systems need not be.

Broad Trend Toward Serial Connectivity

Experts agree that both single-ended and differential parallel I/Os have reached their physical limitations and cannot provide a reliable and cost-effective means for data rates greater than 1 Gbps. Serial I/O provides benefits not only to high-speed but also to low-speed systems. This double benefit has propagated waves of new serial interface standards development.

The inevitable result is the current wide-spread migration toward serial I/O across many segments of the industry, including PC and consumer, storage and servers, communications networking, industrial computing and control, and test equipment.

Serial system interfaces such as PCI Express™, Serial RapidIO™, Infini-Band™, 1 Gb Ethernet, 10 Gb Ethernet XAUI (10 gigabit attachment unit interface), Fibre Channel, Serial ATA, SxI-5, and TFI-5 are all available today, with many more coming to address specific needs.

Serial Tsunami Initiative

Xilinx launched the Serial Tsunami Initiative (www.xilinx.com/connectivity) to sail the crest of the industry move from parallel to serial interfaces, to reduce costs, and to keep pace with current and future bandwidth requirements. The initiative is a vision for delivering a complete suite of serial connectivity solutions – including Platform FPGAs, IP cores, design software and methodologies, reference designs, solution boards, extensive characterization data, and training classes – to enable you to design your next-generation products.

Unlike point solutions, the Xilinx Serial Tsunami Initiative help you surf the surges of multiple, evolving serial standards all the way across devices, IP, and software as you build your systems.

The foundation of the Serial Tsunami Initiative is RocketIO™ technology, which was developed by RocketChips Inc. and acquired by Xilinx two years ago. Today, a dedicated R&D team in the Communications Technology Division (CTD) is wholly focused on improving, developing, and delivering the capabilities that make up the Serial Tsunami vision. Commenting on this strategy, Wim Roelandts, president and CEO of Xilinx, said: “The underlying RocketIO technology that’s making it possible for Xilinx to support multi-gigabit systems is truly ‘rocket science’ – not something you’d want to simply license from an external IP provider. Having the internal expertise is a critical element of our strategy to make serial a mainstream technology by providing designers with a comprehensive, scalable, and cost-effective solution.”

“As the only FPGA vendor shipping platform devices with programmable 3.125 Gbps transceivers and IP cores for key serial interface standards, it’s evident that our approach is paying off,” he added. “Watch for many more exciting developments in the coming months as we continue to extend our market lead in serial connectivity.”

Steve Berry, principal analyst for Electronic Trend Publications, evaluated the benefits of the serial I/O trend and the role Xilinx plays in the movement: “Through its leading technology and well-established strategic partnerships, Xilinx is poised to lead the industry in the transition to serial interfaces. System architects will experience dramatic improvements in bandwidth, pin count, power, and signal integrity.”

Virtex-II Pro Platform FPGAs

Although it is widely accepted that serial I/O delivers significant advantages over parallel I/O methods, until now there was no flexible, cost-effective, general-purpose silicon support. The standards wars do not have clear winners, and the transition path is not obvious.

Virtex-II Pro Platform FPGAs (Figure 1) deliver state-of-the-art serial I/O with as many as 24 RocketIO transceivers embedded in the highest performance FPGA fab-ric in production. The RocketIO transceivers (Figure 2) operate at speeds from 622 Mbps to 3.125 Gbps. The product is available in a wide range of programmable logic densities in 10 devices and several packages. Virtex-II Pro FPGAs support all major emerging serial interfaces such as PCI Express, 1 Gb Ethernet PHY, 10 Gb Ethernet XAUI, Fibre Channel, OC-48, OC-192, and OC-768 SONET for backplanes, and Serial RapidIO.

Virtex-II Pro FPGAs also support parallel interface standards such as SPI-3 (POS PHY Level 3), SPI-4.1 (Flexbus 4), SPI-4.2 (POS PHY™ Level 4), 10 Gb Ethernet Media Independent Interface (XGMII), RapidIO, PCI, PCI-X, CSIX, HyperTransport™, XSBI, and SFI-4.

The Virtex-II Pro FPGA is the only device available today that enables bridging across all these interface classes and generations, making it the ultimate connectivity platform.

Xilinx Tools and Solutions for Serial Connectivity

Using the 3.125 Gbps RocketIO integrated transceivers in Virtex-II Pro FPGAs, Xilinx and its partners are delivering pre-engineered IP cores for serial connectivity protocols. Cores for 1 Gb Ethernet MAC with PHY, 10 Gb Ethernet MAC with XAUI, PCI Express, Fibre Channel, and reference designs for SONET OC-48 backplanes are available now, and more are being added. You can also build higher level protocols using the embedded IBM PowerPC™ processors. Reference designs and evaluation/prototype boards help you verify the performance of transceivers in real hardware.

Designing with parallel I/O meant you were limited to speeds of 33 MHz to 133 MHz. In the serial world, these speeds leap to 622 MHz, 3.125 GHz, 10 GHz, and beyond. This raises challenges with PCB design and signal integrity. Xilinx and leading EDA partners such as Cadence are solving this dilemma with tools such as SPECCTRAQuest™ transmission media and HSPICE™ (highly accurate simulation program with integrated circuit emphasis) models.

Xilinx provides in-depth characterization data (Figure 3) for the RocketIO transceivers for flawless system design using our Virtex-II Pro FPGAs. You will know exactly how your design is expected to operate, and you will be supported every step of the way with best design practices and PCB layout guidelines.

Aurora Reference Design
Aurora is a new, open, lightweight, scalable serial interface provided by Xilinx to help you transition from parallel to serial interfaces. It supports any transport protocol, has a compact architecture, and delivers low latency. A single-lane reference design is available for free download at: www.xilinx.com/aurora. A quad link reference design will be available during the first half of 2003.

Xilinx takes an active role in industry standards organizations – including PICMG, RapidIO Trade Association, NPF, OIF, PCI-SIG, XFP, SMPTE, and others – with the goal of providing complete solutions synchronized with the availability of new standards. An example is the industry’s first PCI Express core, which Xilinx released on the same date that the PCI-SIG ratified the specification. [Ed. note: See “Xilinx Technology Enabled Instant Deployment of Real-PCI Express” in this issue.]

The Serial Tsunami Initiative also offers several levels of training about working with serial technologies. These range from an online introduction to in-depth face-to-face classes. In addition, design support and services are available from experienced designers within Xilinx Design Services.

Manage Interoperability
The multiplicity of available and emerging serial standards is reflected in the range of interfaces embraced by available ASSPs. Your optimum design could easily incorporate multiple ASSPs equipped with a variety of interfaces. Xilinx and ASSP vendors work closely together to ensure interoperability with Virtex-II Pro features and electrical I/O standards as well as interface IP cores jointly verified in hardware. [Ed. note: For a discussion of ASSP and Virtex-II Pro FPGA inter-operability, see “Virtex-II Pro Platform FPGAs Deliver Proven Interoperability” in this issue.]

Bridge Across Any Standard
The leading parallel standards are not going to vanish overnight, and you might find it necessary to accommodate an older parallel standard in a design that is intended to promote a newer serial standard. So how do you manage the transition? Virtex-II Pro FPGAs have solved this for you by supporting both serial and parallel interfaces within the same FPGA. Xilinx delivers IP cores and reference designs to interface with parallel standards such as 10 Gb Ethernet XGMII, RapidIO, SPI-3, SPI-4.1, SPI-4.2, HyperTransport, PCI, PCI-X, CSIX, XSBI, SFI4, and many others.

With Virtex-II Pro FPGAs you can bridge across parallel and serial interfaces to make a seamless transition. Plus, you can continue to interface with the ASSPs that best suit your needs based on their function, not on their interface support.

Case Studies – Serial vs. Parallel

Serial helps you break the bandwidth bottleneck with higher data rates using fewer pins. This lowered pin count delivers many advantages over traditional parallel implementations.

• Low device pin counts: With fewer pins per connection, you save costs from small board real estate, smaller packages, fewer PCB traces and layers, and even smaller connectors.
• Expansion and scalability: High-speed serial pipes scale to support higher data rates as needs change.
• Improved EMI and noise immunity: With embedded clock-data mechanism that is serial vs. wide parallel data and clock, you get higher clock rates at lower EMI, noise, cross talk, and skew.
• Physical interfaces: Serial I/O physical interfaces can also drive long PCB traces on backplanes or even external cable (copper or optical).

One obvious way to analyze the costs and benefits of I/O interfaces is to compare performance per pin. Let us take a look at two examples – PCI Express vs. PCI, and 10 Gb Ethernet XAUI vs. XGMII.

Case 1 – PCI and PCI-Express
PCI is a higher bandwidth, parallel, sharedbus standard, while the PCI Express protocol is a new serial version. A 5-client communication example (Figure 4) contrasts the two standards:

• A 32-bit/33 MHz PCI interface requires (32 bits x 33 MHz = ~1 Gbps) total bandwidth that would be shared among all five clients (5 x 50 pins = 250 pins).
• The PCI-Express interface operates at 2 Gbps data rate in each direction, delivering 4 Gbps full-duplex bandwidth over just four pins (that is, two differential pairs) for each point-to-point connection. The total aggregate bandwidth provided in the same 5-client configuration is 80 Gbps (4 Gbps/connection x 4 connections/client x 5 clients = 80 Gbps).

Case 2 – 10 Gigabit Ethernet XGMII and XAUI
XGMII is a full-duplex interface between the MAC and PHY layers. XAUI is a serialized version of this interface (Figure 5).

• XGMII is a full-duplex, parallel interface operating at 312.5 Mbps per wire using 74 pins for data, clock, and control. Its data rate is 10 Gbps each way. Due to signal count, skew, and other problems, XGMII fails to support multiple interfaces in a single chip or routes longer than a few centimeters. Hence, it is restricted to be only a chip-to-chip interface and has a maximum FR4 trace limitation of two inches.
• XAUI is a 4-lane, full-duplex, serial interface, with each lane running at 2.5 Gbps data rate (3.125 Gbps baud rate). It requires 4 differential signal pairs in each direction and hence, 16 pins in total, delivering 10 Gbps aggregate data bandwidth. Automatic de-skew and pre-emphasis allows XAUI to route as much as 20 inches FR4 on PCBs, backplanes, and even cable. Its low pin count makes it highly scalable.

Fewer pins, higher bandwidth, scalability, and significant cost savings are all driving the move to serial.

Conclusion

The Xilinx Serial Tsunami Initiative is revolutionizing system architectures. State-of-the-art serial I/O delivers scalable, high-bandwidth at low cost. As the industry rapidly moves to serial connectivity, and away from current parallel interface schemes, you must either sink or swim. Xilinx and Virtex-II Pro Platform FPGAs offer a whole boatload of serial solutions from the initial concept to the finished product. Check it out at: www.xilinx.com/serialsolution/.

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