The Xilinx “Adaptive I/O” solution enables rapid prototyping, enhanced diagnostic testing, and in-system performance optimization for high-speed serial I/O designs.

The shift to high-speed serial I/O technology has enabled designers to push the performance of systems well beyond that of traditional parallel bus-based architectures. Multi-gigabit serial links are capable of transmitting data at substantially greater speeds, with significantly lower power, and with a fraction of the pins required for system-synchronous (common clock) or source-synchronous (clock forwarding) schemes.

However, with all the advantages of serial I/O technology, you must address a number of new design challenges when integrating high-speed serial links into your design. Board design, for example, becomes a more involved issue when dealing with signal integrity and transmission line effects of multi-gigabit serial signals. In addition, standards compliance and interoperability testing require new characterization techniques and additional resources during the development process.

The Xilinx “Adaptive I/O” solution for the Virtex-II Pro™ family of Platform FPGAs gives you the power and flexibility to meet these serial I/O design challenges head-on. Leveraging the combination of the RocketIO™ multi-gigabit transceivers (MGTs) and the IBM PowerPC™ 405 embedded processor core, the Adaptive I/O solution gives you the performance and system-level management functions you need to accelerate the development of your high-speed serial design.

The solution is delivered in the form of three pre-engineered reference designs that can be easily integrated into your existing design environment to provide rapid prototyping ability, enhanced characterization and diagnostic testing, and in-system performance optimization of your high-speed serial links. Although the reference designs take advantage of the integrated processor in the Virtex-II Pro device, no PowerPC or C-programming expertise is required to use the Adaptive I/O solution.

Multi-Gigabit Signal Integrity

Designing with multi-gigabit serial I/O technology requires greater attention to issues that affect signal integrity, such as attenuation, noise, and reflections. At multi-gigabit frequencies, board traces behave like transmission lines, introducing the need for a more detailed understanding of the signal topologies and characteristics of the transmission medium. Jitter effects, dielectric losses, and impedance matching issues must all be carefully considered to ensure reliable data transfer across a serial link at the intended baud rate.

Serial I/O technology provides benefits at various levels within a system, enabling the creation of high-speed links from chip to chip, board to board, and box to box. Clearly, signal topologies and even the transmission medium can vary significantly depending on the type of application. The complexity of the design challenge and level of signal integrity analysis required will also vary accordingly. For example, transmitting over several feet of coaxial cable presents different challenges than transmitting over a few inches of FR4 laminate board.

Consider the example of a serial backplane (Figure 1) in which the distance a signal must travel can change substantially depending on which slot a board is plugged into. The signal attenuation and deterministic jitter imposed on the longer backplane trace will be greater than on the shorter trace. In scenarios such as this, it is often desirable to modify or “tune” the drive characteristics of the MGT transmitter to match the characteristics of a particular signal path, ensuring the highest possible signal quality and reliable recovery of the data at the receiver end.

Solving the Backplane Dilemma

The RocketIO MGTs in Virtex-II Pro devices include many advanced features to simplify the development of serial I/O-based systems. The MGT blocks are composed of two distinct sub-blocks (Figure 2): the physical media attachment (PMA) block and the physical coding sub-layer (PCS) block. The PMA is responsible for the serialization and deserialization (SERDES) of the data stream as well as the actual physical interface for the MGT transmitter and receiver. The PCS interfaces with the FPGA fabric and manages encode/decode functions, clock synchronization, clock correction, and channel bonding operations.

Among the list of other common SERDES functions, there are two programmable features contained within the MGT blocks to optimize transmission over a wide variety of signal topologies and transmission media:

• Programmable differential swing control
• Programmable pre-emphasis.

Programmable Pre-Emphasis
High-speed serial signals experience significant attenuation (signal loss) due to the “skin effect” and dielectric losses of the transmission medium, particularly over longer distances. Pre-emphasis is a technique whereby the highest-frequency components of the serial signal are boosted to compensate for these losses, significantly extending the distance the signal can be reliably transmitted over a given type of conductor.

Virtex-II Pro MGTs have four levels of programmable pre-emphasis (from 10% to 33%) selectable through the RocketIO primitive attribute TX_PREEMPHASIS. At maximum pre-emphasis, RocketIO MGTs are capable of transmitting a 3.125 Gbps serial signal error-free over more than 40” of standard FR4 printed circuit board material (Figure 3).

The Adaptive I/O solution solves the backplane dilemma by giving you the ability to dynamically adjust the programma-ble swing control and pre-emphasis levels of the MGTs in response to changing signal topologies, while leaving the rest of the FPGA design unchanged. For example, referring again to Figure 1, the Virtex-II Pro MGT transmitter can be automatically configured to have different swing control and pre-emphasis settings in response to the changing trace length associated with each slot location.

Application Note XAPP660 (www.xilinx.com/xapp/xapp660.pdf), with complete reference design files, provides you with an entirely self-contained solution for dynamic configuration of the MGT swing control and pre-emphasis attributes (Figure 4). The PowerPC 405 core is used to perform reconfiguration of the MGT attributes via the internal configuration access port (ICAP), an interface similar to SelectMAP, which allows the FPGA configuration logic to be accessed over general interconnects inside the device.

After power-up and initial configuration with a base FPGA design, the PowerPC processor reads a 4-bit slot ID register to determine the swing control and pre-emphasis settings that should be assigned to each MGT for the given signal topology. The PowerPC core then modifies the MGT attributes by managing a partial reconfiguration of select configuration bits over the ICAP interface, leaving the rest of the FPGA design unchanged.

The slot ID can be a static code delivered from the backplane or a dynamic value driven by internal logic or another device. The MGT attribute settings for each slot ID value are predefined with simple modifications to a “C” file array structure. The end result is that the MGTs can adapt to up to 16 different signal topologies automatically and provide optimal signal transmission without the need for separate bitstreams. The use of the PowerPC 405 core to manage the MGT attribute modifications results in a very resource-efficient design. The total solution consumes only 67 slices (about 2% of an XC2VP4 device), and can thus be easily integrated into almost any Virtex-II Pro design.

Enhanced Characterization and Diagnostic Testing

In addition to managing the signal integrity aspects of multi-gigabit serial I/O design, significant time and resources can be spent on standards compliance, interoperability testing, and general characterization of the serial links during the development process. Furthermore, multi-gigahertz oscilloscopes, bit-error rate test (BERT) modules, and other required test equipment can quickly consume a good portion of your program budget.

The Adaptive I/O solution again offers a pre-engineered solution for simplifying the development and reducing the overall cost of MGT-based designs. Application Note XAPP66 (www.xilinx.com/xapp/xapp661.pdf), with associated reference design files, describes the Xilinx bit-error rate test (XBERT) module for enhanced characterization and diagnostic testing (Figure 5). The XBERT module includes a pattern generator capable of generating eight different pseudo-random bit sequence (PRBS) patterns as defined by ITU-T (International Telecommunication Union-Standardization Sector) Recommendation 0.150. It also includes a built-in error detector and frame/bit-error counters for tracking the total number of transmitted frames and total number of associated bit-errors.

The XBERT module is controlled and monitored by the PowerPC core over the processor local bus (PLB) interface. In addition, the PowerPC core reads the status of the frame and bit-error counters and then transmits this information to the PLB-attached universal asynchronous receiver transmitter (UART). Using a standard serial cable connection to a PC, the UART can communicate with a simple PC terminal program such as Hilgraeve Inc.’s HyperTerminal, giving you the ability to control the bit-error rate testing from your keyboard and see the test results continuously updated on your PC screen.

Using the results from the XBERT module, a practical bit-error rate (for example, less than 10^-12) can be calculated for your multi-gigabit serial links. And, because the XBERT is a soft implementation built from FPGA logic resources, it can be used for characterization or diagnostic testing and then removed from the final design. The XAPP661 reference design solution gives you the ability to perform sophisticated bit-error rate testing more efficiently and at a fraction of the cost of other solutions.

Putting It All Together

The XAPP660 reference design provides the ability to automatically adapt the MGT transmitter attributes to meet changing signal topologies or other system requirements. And XAPP661 enables enhanced characterization or diagnostic testing of serial links with an interactive user interface.

However, the Adaptive I/O solution takes things one step further. Application Note XAPP662 (www.xilinx.com/xapp/xapp662.pdf) combines the XBERT characterization module of XAPP661 with the MGT partial reconfiguration capability of XAPP660 to provide a complete MGT development platform for real-time performance optimization, adaptive system calibration, and field diagnostic testing.

The XAPP662 reference design adds an ICAP controller interface to the internal PLB of the system described in XAPP661, adding the ability to modify the MGT differential swing control and pre-emphasis settings during characterization and diagnostic testing (Figure 6). Using a standard intellectual property interface (IPIF) module available from Xilinx, the ICAP controller module is easily integrated into the PLB-based system.

With this solution, you have the power to perform an iterative loop, alternating 00 Figure 3 - 3.125 Gbps over 44 inches of FR4 with 33% pre-emphasis between MGT attribute changes and bit-error rate testing through a command line interface on your desktop PC. The end result is a complete solution for real-time performance optimization and reliability testing of your MGT serial links.

Portions of the XAPP662 reference design can also be easily integrated into your final design. The IPIF-to-ICAP interface module, for example, can be used in any PLB- or OPB- (on-chip peripheral bus) based system to provide MGT attribute reconfiguration under control of the PowerPC core. This can be a preferred solution to XAPP660 for systems that already incorporate a PLB or OPB bus structure. In addition, any in-system communication link can interface to the on-chip UART, introducing the possibility of remote system upgrade or field diagnostic testing.

Managing the Product Life Cycle

Together, the three components of the Xilinx Adaptive I/O technology provide you with solutions to help you manage your high-speed serial systems in all phases of the product life cycle. In the development phase, the ability to perform real-time performance optimization with interactive control over MGT attributes and the XBERT module provides you with rapid prototyping and efficient characterization.

In your fielded production design, the MGT partial reconfiguration controller of XAPP660 or XAPP662 gives you the power to automatically adapt your MGT transmitter characteristics in response to different signal topologies or changing system environments on the fly. This ensures that every link is optimized for performance and minimum bit-error rate without the need for multiple bitstreams or external components.

Lastly, the Adaptive I/O solution gives you the ability to perform in-field system calibration or diagnostic testing to ensure your end product is maintained for maximum reliability and performance.

Conclusion

The Xilinx Adaptive I/O solution enables rapid prototyping, enhanced characterization, and in-system performance optimization of your multi-gigabit serial I/O designs. The combination of RocketIO MGTs and the IBM PowerPC 405 core provides you with a complete platform for developing, optimizing, and delivering world-class, high-speed serial solutions.

To learn more about the three reference designs that make up the Adaptive I/O solution, visit www.xilinx.com/search/vsearch.htm.

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