The Virtex-II and the Virtex-II Pro EasyPath solutions are a cost-effective alternative to ASIC conversion – saving you money while significantly decreasing your time-to-market.

Once a working prototype is developed, designers using high-density FPGAs need a risk-free method of reducing the cost of components used in their end-market products and systems. The traditional ASIC approach is expensive and error prone. The designer typically relies on an ASIC conversion methodology provided by either the FPGA or the ASIC supplier. These methods are supported by a wide range of claims for conversion accuracy and performance. Typically, 30 to 40 weeks is required to accomplish such a conversion for mass production.

Xilinx attacks this problem head-on with our introduction of the Virtex-II EasyPath™ series solutions, including a Virtex-II Pro™ version, as the newest member of the Virtex™-II family of Platform FPGAs. The EasyPath solution slashes the conversion time to 10 to 12 weeks (Figure 1), and delivers a 30% to 80% cost reduction without risk and without additional investment of engineering time or other resources.

Traditional Conversion: Trial and Error

Conventional conversions require direct time and expense for the services of the ASIC manufacturer for fabrication masks and test programs, and for the engineering cost of verification and simulation. When the completed system is transferred into production, further system engineering time and expense are needed to requalify the final production system with this new ASIC.

As systems become faster, timing and clocking budgets are tighter, and any slight change in critical paths brought about by ASIC conversion can cause timing mismatches and race conditions. All of these factors introduce substantial risk of delay and escalating cost.

Risk-Free, Quick, and Easy

The Virtex-II and Virtex-II Pro EasyPath FPGAs emerge from the conversion process ready for full production without any need for a requalification or proof of performance that would normally be required of new ASIC silicon. EasyPath silicon is identical to the FPGA prototype, with the logic and routing resources used by the customer design completely tested for functionality and performance at speed.

Streamlined Process
Once the design is settled and the qualification completed, you can simply submit four design files (Figure 2), which are standard outputs from any Virtex-II and Virtex-II Pro design.

The EasyPath product is tested for performance and functionality using the same techniques as those applied to the prototype FPGA. Designers order the same speed grade, package, and density as they did for the original FPGA. Typical lead times for production quantities range in weeks rather than months – from the engineering confirmation of the design submittal to full production silicon (thousands of units).

There is no need for the customary first article testing and no risk of the delays that result from multiple spins of ASIC silicon.

Test Coverage
The manufacturing test of EasyPath silicon is based on a foundation of proven FPGA test techniques that assure complete testing of the customer design.

Typical ASIC testing relies on the completeness of vectors generated by the customer or the ASIC supplier. The ASIC sup-plier works in conjunction with the design-er to cover all the possible test cases with vectors to assure correct operation. In contrast to this approach, EasyPath testing is based on instrumenting and test-ing all of the resources used by the cus- tomer design, as well as testing critical structures at speed. Using multiple bit-stream loads, each resource is instrumented using a library of Verifault™ verified test designs (Figure 3). The resources used in the EasyPath design are matched against this proven test library, with each routing resource tested using “source” and “load” techniques (Figure 4). The “source” provides the stimulus, and the “load” evaluates the response. The EasyPath solution takes advantage of some of the unique architectural features of the Virtex-II and Virtex-II Pro FPGAs. When testing routing, for example, you can allow unused routing resources to be tied to a known state to test for shorts. As for complicated circuitry such as block RAMs and multipliers, we use multiple bitstreams to instantiate built-in self-test (BIST) structures (Figure 6) designed to thoroughly test these complex circuits.

Error detectors (Figure 5) check for the correct operation of each circuit. Critical resources within the device are speed tested using standard FPGA techniques to guarantee the device operates at the desired speed grade.

Conclusion

The Virtex-II and Virtex-II Pro EasyPath solutions eliminate your risk, and give you complete control over the expense of converting to a lower cost solution for advanced systems. Now you can reduce total system cost without the need for additional engineering resources. You won’t have to requalify the system for new silicon, or worry about the cost and delay of ASIC silicon respins. You can confidently predict the crossover point for realizing the cost savings of the conversion.

In light of current market pressures and tight inventory management, a conventional ASIC will not always be the optimum cost reduction solution. The Xilinx Virtex-II Pro EasyPath solution provides you with a risk-free, rapid, and easily implemented cost reduction alternative. Check it out at www.xilinx.com/easypath/.

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