By minimizing wire crossing and printed circuit board route complexity, DesignF/X pin assignment software reduces routing layers and enables your systems to run faster and come to market sooner.

According to the International Technology Roadmap for Assembly and Packaging, sponsored by International SEMATECH, the package pin count for high-performance ICs is expected to reach 4,009 by year 2007. With densities of this magnitude, proper pin assignment is essential to maximize the component, board, system performance, and to deliver products on time and on budget. The Xilinx Serial Tsunami Initiative addresses density-related problems from the FPGA component perspective, but you also need the right board-level EDA tools. Most of today’s EDA board-level tools focus solely on schematic and layout issues. In doing so, they fail to address many of the complex problems – such as board performance, cost, and schedule slippage – that are created by sub-optimal pin assignment.

In addition to enhancing performance by reducing routing layers, automating pin assignments at the front end of the design process gives you more time for signal integrity analysis, functional simulation, and even system packaging activity. The end result is higher quality products with significant reductions in design time, engineering costs, and product manufacturing costs.

The DesignF/X™ automated design and optimization tool from PAI (Product Acceleration Inc.) helps you analyze and optimize the component pin assignments very early in the product development cycle – during concept development, device selection, early component architecture and placement, and early FPGA device floorplanning. The DesignF/X tool helps shorten development time and time-to-market, improves the performance of the finished product, and reduces the costs of development and of the finished product as well. DesignF/X Benefits

The DesignF/X tool suite enhances product feasibility, reduces engineering time and costs, and improves operational metrics.

Product Feasibility
Often, high-density PCB routing challenges are solved through thinner traces combined with extremely small, blind, or buried vias and increased PCB layers. These solutions, however, can result in significantly degraded system performance and forced operation at lower system clock speeds. In some cases, the degradation is so bad it results in the loss of market relevance for a product. With the DesignF/X tools, these issues are avoided through earlier, smarter, and faster analysis and optimization of pin assignments on critical system components. In turn, this enables fundamental product viability and increases the odds of market success.

Engineering Costs and Timelines
Engineering costs are driven by individual task lengths, inter-task relationships, and labor costs. The use of FPGAs clearly implies a desire to control engineering costs. However, traditional approaches require the FPGA designer to interact with and wait for task completion by a systems hardware designer and a PCB layout engineer. Only then can the FPGA designer analyze and optimize pin assignments, using a manual and iterative process. These delays and iterations affect the direct cost of the activities, creating unnecessary task dependencies, forcing extensive change management overhead, and impacting the overall project momentum.

The DesignF/X tool suite employs intelligent algorithms to create an accurate impact analysis and optimize pin assignment early, before you spend time creating symbols, schematics, and developing the PCB layout. Consequently, the FPGA designer handles board-level issues regarding pin assignment directly, without the task and process delay imposed by traditional processes. The result is an immediate improvement in project engineering costs and timelines.

Operational Metrics Apart from the costs of R&D, other key operational metrics that determine product success are the cost of production and time-to-market.

The choice of an FPGA-based design approach implies that time-to-market is a key operational metric for the success of your project. However, poor pin assignment can result in PCBs that are more expensive to manufacture, with up to a 10% cost increase with each additional board layer. In addition, increased PCB layer counts may result in longer order cycles and a narrow supply base. This becomes extremely important when layer counts rise above 24, and critical at more than 40 layers, at which point the PCB itself represents a significant portion of the overall system cost.

By avoiding increased order cycles and extended development cycles, DesignF/X tools help you gain significant time-to-market advantages. By helping to reduce the complexity of the PCB and its layer count, the DesignF/X software lets you reduce recurring product costs, improve order cycles, and expand the pool of available suppliers.

Figure 1 compares the cost of designing a product with – and without – the DesignF/X package. In this example, the DesignF/X tool suite enables an organization to reduce costs by nearly $27,000 per design and shorten product design cycle time from 25 weeks to just over 16 weeks. This reflects a greater than 33% improvement in margin per design and a savings of more than eight worker-weeks. By using DesignF/X tools early in the design process, you can help avoid costly iterations due to improper pin assignments and reduce the time of your FPGA design flow iterations to nearly zero.

Design Flow Using DesignF/X

Begin by importing your component information or creating it rapidly from your datasheet or ASCII pin file. You then specify the connectivity between the target FPGA and other major components, as well as their approximate placement. This process includes a definition of pin/signal mobility and basic constraint information.

The DesignF/X software then performs a “situation analysis” based on various combinations of component connectivity and placement, resulting in optimized pin assignments. The optimization is performed in terms of the board itself and of the system as a whole, with special attention paid to detecting and reducing wire crossing. Figure 2 illustrates the effectiveness of DesignF/X detection and reduction of wire crossing.

Once you are satisfied with the results, you can create output files consisting of optimized component pin assignments and related reports. These individual component pin assignments can then be used as pin assignment constraints for the internal design of those components.

Original pin assignments can be written in the Xilinx PAD file format. The DesignF/X program outputs the optimized pin assignments in the corresponding format, enabling DesignF/X software to fit seamlessly into your FPGA design flow with minimal disruption to existing processes.

Future releases of the DesignF/X tool suite will support bidirectional data exchange with Xilinx PACE software to create pin and area constraints. In this case, an NGD file is used as input to PACE. Any additional FPGA pin and area constraints can then be developed using PACE and saved for use in the Xilinx place-and-route flow.

Figure 3 illustrates how DesignF/X-generated pin assignment constraints can be used easily in an FPGA design flow.

Conclusion

Unlike other EDA board-level design tools – which focus on schematic and layout issues – the DesignF/X suite from PAI provides you with what you need to reduce design time and costs through pre-layout pin optimization. With an intuitive user interface, Java-based design, powerful algorithms, and accurate analysis capabilities, DesignF/X software enhances the quality, performance, and cycle-time parameters of board design projects. The PAI product suite is designed to coexist within existing methodologies – protecting your investment in tools, skills, and processes. For more information about DesignF/X and PAI’s software solutions, visit www.prodacc.com or email sales@prodacc.com.

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