The same breakthroughs that make FPGAs competitive with ASICs also impose design and verification challenges that require advanced methodologies and debug capabilities. Mentor Graphics’ Precision Synthesis tool provides them.

In the fast-moving world of programmable logic, EDA vendors face the persistent challenge of creating design tools and methodologies to keep pace with the increasing complexity and capacity of silicon.

ASICs have historically provided a cost-effective solution for the electronics industry; this technology is responsible for considerable growth and innovation. The popularity of ASIC technology has provided the driving force in the EDA industry and dictated the direction for software development. ASIC development is, however, moving beyond the reach of many mainstream designers due to high upfront (NRE) charges and a longer time-to-market. FPGAs are filling this void and will become the dominant approach for designers and the new driving force in the EDA industry.

FPGA Growth

FPGA design methodology has many advantages. You control the entire design and layout processes. Design cycle times are faster, photo-mask costs are non-existent, and there are no minimum order restrictions. On the other hand, the low performance, comparatively smaller gate densities, and high unit costs of FPGAs have historically relegated them to small, low-volume designs. ASICs claimed the remainder of the market.

Xilinx is overcoming these market barriers by developing reconfigurable, system-level FPGAs such as the Virtex-II Pro™ Platform FPGA, which integrates embedded microprocessor cores, memory, and hard and soft macros. These features provide you with the benefits of reduced system-development times, improved power consumption, increased volume, and expanded board space, as well as the flexibility to make changes right up to production time. These dramatic technological breakthroughs, however, add design and verification challenges and require new methodologies and debug capabilities.

For designers to take full advantage of FPGA technology, the supporting software tools must be capable of solving designers’ toughest challenges. Mentor Graphics introduced its Precision™ Synthesis platform to solve this new set of problems.

Precision Synthesis Concepts

Three major considerations drove the development of the Precision Synthesis platform’s architecture:

1. Intuitive user interaction
2. Excellent Quality of Results (QoR)
3. Advanced analysis.

The Precision Synthesis platform also offers push-button synthesis flow without compromising results or flexibility. This ease-of-use feature was achieved by replacing user-configured synthesis options with automated configuration. Optimization algorithms configure options based on an analysis of a design against its constraints, thus eliminating the need to specify effort levels or optimization “goals.”

Intuitive use can be enhanced by utilizing industry standards and knowledge whenever possible. We adopted, for example, the Synopsys Design Constraint (SDC) format for defining timing constraints. As many ASIC designs are now completed in FPGAs, the SDC format eases the migration of designs between the two design environments.

Excellent Quality of Results

The Precision Synthesis tool includes a suite of unique algorithms called Architecture Signature Extraction (ASE) optimization that automatically focuses specific optimizations on those areas of the design that are most likely to hinder overall performance, such as finite state machines (FSM), cross-hierarchical paths, or paths with excessive combinational logic. The ASE technology uses an automated, heuristic approach to deliver smaller and faster designs without iterative manual user intervention.

The Precision Synthesis platform’s ASE technology takes full advantage of Xilinx device features by providing the smallest design that meets your target frequency. This saves you time by reducing design iterations, and money by helping you fit into smaller devices or lower speed grades in the process.

Advanced Analysis

FPGA devices are now being used to implement highly complex designs for a wide range of applications. The complexity of large systems results from the detailed timing and clocking requirements being designed into these devices. This timing complexity can lead to excessive design iterations or even undetected timing problems affecting printed-circuit-board debug.

To solve these new timing issues and guarantee a reliable design, the Precision Synthesis platform includes a timing engine and design analysis capabilities. Its PreciseTime™ timing engine provides a completely interactive, standalone timing analysis environment designed to handle the most complicated clocking schemes with speed and accuracy. The PreciseTime engine’s capabilities extend beyond timing analysis to include:

• Reports of internal clocks, including clock propagation information through simple gates, dividers, and DCMs
• Reports of missing constraints that prevent comprehensive timing analysis
• Reports of timing paths that cross asynchronous clock domains (These reports help you verify clock isolation or the existence of metastable safe synchronization logic.)
• Powerful schematic viewing with schematic-fragment-generation capabilities and multiple critical-path viewing (Figure 2).

First-time success on your printed circuit board requires a fully and accurately constrained design during synthesis; PreciseTime was designed to do just that.

Next-Generation FPGA Synthesis

The FPGA synthesis domain is rapidly expanding beyond the RTL space to encompass the architectural and physical realms. This expansion will produce significant gains in both designer productivity and chip performance. Designers will require tools with powerful algorithms for optimization at each level of abstraction. They will benefit from a seamless methodology that allows easy migration throughout each phase of the design.

The Precision Synthesis product designation represents a synthesis technology platform that encompasses a family of synthesis products created by Mentor Graphics to address high-end FPGA design issues from different levels of abstraction.

Built to keep pace with the ever-changing programmable logic world, the Precision Synthesis platform is a choice worth considering for next-generation FPGA implementations. By incorporating an intuitive user interface, excellent QoR, and unparalleled accuracy, it can handle the toughest FPGA designs.

Mentor Graphics is committed to provide you with the latest set of EDA tools to enable electronic design innovation. For more information about the Precision Synthesis platform or Mentor Graphics’ complete FPGA-design product family, visit www.mentor.com/fpga/.

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