Second-generation Broadband Fixed Wireless Access standards are still coalescing – but all require high-performance signal processing power. You can meet your processing goals while maintaining standards flexibility by using Virtex FPGAs.

Broadband Fixed Wireless Access (BFWA) technology standards are consolidating behind the IEEE 802.16 specification in the U.S. and the ETSI BRAN (European Telecommunications Standards Institute Broadband Radio Access Networks) specification in Europe. This convergence makes BFWA technology commercially attractive, particularly as a flexible, cost-effective, 3G (third-generation) cellular backhaul solution.

Both standards take broadly similar approaches to solving the Quality of Service (QoS) and bandwidth-utilization limitations experienced by first-generation BFWA services. However, both standards demand greater signal processing performance than conventional DSPs can deliver today, which leaves the door open for developing custom hardware to boost performance.

The BFWA market remains difficult to predict, especially in the domestic and SME (small and medium enterprise) sectors. Some observers, for example, believe standards must harmonize further to make the technology viable. Therefore, developers must find ways to achieve hardware acceleration without compromising flexibility, time to market, or cost-effectiveness.

System Challenges
The differing requirements of 3G backhaul and residential/SME applications mean that, as a designer, you must create access solutions that are capable of handling a wide range of services. These include legacy services such as time division multiplexing (TDM), IP (Internet Protocol), and VoIP (Voice over Internet Protocol). A variety of backhaul requirements must also be accommodated, including ATM and packet-based protocols. In other words, your design must have enough flexibility to efficiently carry any traffic type.

Maintaining QoS and delivering 99.999% availability, or "five 9s," is made more difficult by environmental effects such as rain, obstructions, or other non-line-of-sight conditions. Both the IEEE and ETSI standards have introduced adaptive coding and modulation algorithms that make the best use of the available bandwidth under favorable link conditions, and they invoke a more reliable alternative to maintain availability under unfavorable link conditions. Co-channel interference also acts to degrade link quality, and both standards address this issue as well.

A wireless access system may be presented with multiple con-nections per terminal, multiple QoS levels per terminal, and a large number of statistically multiplexed users. As a result, second-generation systems demand an extremely high-performance, scalable, signal processing platform designed for wireless processing and dataflow.

Physical Layer Design
While the Media Access Control (MAC) layer handles algorithms relevant to the various traffic classes, complex adaptive coding and modulation are performed at the PHY (physical) layer.

The PHY specifications for IEEE 802.16 and ETSI BRAN standards establish a burst specification that allows both time-division duplexing (TDD) and frequency-division duplexing (FDD). Both TDD and FDD support adaptive burst profiles in which transmission parameters relevant to modulation and coding may be assigned dynamically on a burst-by-burst basis. Further complexity is added by including support for half-duplex FDD subscriber stations (which may help to reduce the cost of subscriber equipment because they do not simultaneously transmit and receive).

Variable burst profiles require extensive processing resources, including Reed-Solomon forward error correction (FEC) with variable block size and error correction capabilities. Moreover, FEC is combined with 16-state quadrature amplitude modulation (16-QAM) or 64-QAM in both ETSI BRAN and IEEE 802.16. ETSI BRAN also defines 4-QAM.

A PHY implementation for either standard integrates transceiver and CODEC (coder/decoder) functions as well as backplane interfaces and data queuing. This implementation calls for complex mixers, frequency synthesizers, mapping capability, automatic gain control, and access point synchronization in the transceiver. Additional CODEC blocks include: Viterbi and convolutional coding; interface buffering; PDU header controls and scramble/descramble; and MUX/DEMUX (multiplexer/demultiplexer) functions. Additional interfacing and data-queuing functions include frame formatting, cell queuing, and lookup or PDU overhead formatting.

As a result, ETSI- or IEEE-compliant base stations must integrate extensive processing capabilities, many of which you can perform in hardware.

Hardware Acceleration
In both second-generation BFWA standards, the algorithmic complexity of the PHY layer in particular has accelerated faster than Moore’s law can empower DSPs to keep pace. Still, a software-reconfigurable solution is desirable given the current uncertain market conditions. Market projections are under constant review, and some manufacturers believe further harmonization of standards must take place before the true potential of BFWA will be realized.

All of these factors make it extremely difficult to plan an ASIC development with confidence. These factors also make creating the ICs for standardscompliant equipment a signifi-cant challenge, especially if you want to avoid the fixed engineering development costs.

On the other hand, high-speed FPGAs allow you to create custom hardware and exploit the massive parallelism needed to meet performance goals without sacrificing flexibility. You can also achieve high integration by implementing DSP functions alongside protocol translation, glue logic, and other system functions. The Virtex™-II and Spartan™ FPGA families also provide a wealth of processing resources, including Xilinx MicroBlaze™ soft processor cores, as many as four embedded IBM PowerPC™ cores (in Virtex-II Pro™ Platform FPGAs), and user-selectable I/Os.

These resources combine well with large IP (intellectual property) libraries, through which Xilinx offers functions such as Viterbi, turbo-product coding, and other off-the-shelf functions.

FPGA Implementation
Figure 1 shows a block diagram for an ETSI-compliant BRAN PHY layer. You can create the design represented here with either two Virtex-II XC2V3000 FPGAs or one XC2V6000.

Transceiver Design

The access point transceiver shown in the diagram includes a Hilbert Transform decimator and interpolator and complex mixers running at around 100 Mbps, or double the symbol rate. You can implement these using the Xilinx System Generator tool, exploiting block RAM and embedded multipliers available in the Virtex architecture as well as its extensive logic resources and look-up tables (LUTs). The mapper function uses block RAM, multipliers, and LUTs to perform LUT-based mapping.

Additional major functional blocks include complex variable decimation and interpolation (CVD/I), linear interpolated digital frequency synthesis, and access point synchronization. You can easily build all of these functions using the XC2V3000/6000’s plentiful block RAM, multiplier, and LUT functions.

CODEC

When designing the CODEC, the combination of Virtex high-speed processing performance and off-the-shelf IP is especially powerful. You can implement a standard Viterbi decoder directly in the Virtex-II architecture using approximately 1,000 slices and two block RAMs. Supporting OC3 (Optical Carrier 3 – 155 Mbps) data rates and higher, the Viterbi decoder implementation offers fully synchronous two-clock or one-clock versions to reduce latency, size, and power dissipation. Because the system-code rate for ETSI BRAN and IEEE 802.16 varies, the decoder also allows you to change puncturing on the fly by using control bits generated from data formatting. The decoder is available as VHDL source code or as a fixed netlist from the Xilinx LogiCORE™ IP program.

Both BFWA standards call for Reed-Solomon forward error correction with variable block size and error correction capabilities. We have modified the standard Xilinx Reed-Solomon IP core to meet the required frame duration and symbol rate, and to reduce latency below 92 byte periods. You can also implement convolutional decoding and encoding using standard Xilinx IP cores. The ETSI BRAN specification includes headroom for optional Turbo product codes, which are also readily available as complete IP cores from Xilinx.

At the Backplane

The Virtex-II XC2V3000/6000 devices can also implement backplane interface and data queuing functions by using the standard Utopia2 (Universal Test and Operations PHY Interface for ATM Level 2) backplane interface IP core. Furthermore, you can custom-define a state machine to perform functions such as scheduling and timing in about 200 slices of the XC2V3000/6000 devices. With all of this functionality, you still have plenty of block RAM and logic resources for queuing, overhead formatting, and header processing.

Conclusion
New-generation standards for broadband fixed wireless access have helped make the technology commercially attractive. But considerable uncertainty remains regarding future standards and markets. This uncertainty demands flexible, adaptable solutions.

At the same time, to answer the QoS and availability limitations of first-generation systems, second-generation standards require processing power beyond the capabilities of conventional reconfigurable DSPs. Xilinx FPGAs deliver the flexibility and raw DSP performance you need as well as the extensive IP cores and engineering support to solve these diverse challenges.

For more information, visit these websites:

• Xilinx Wireless Networks Solutions – www.xilinx.com/esp/wireless_networks/index.htm
• IP cores suitable for BFWA – www.xilinx.com/ipcenter/.

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