A new low-cost development kit for Xilinx CoolRunner-II CPLDs helps experts and novices alike get the most from their designs.

The new CoolRunner™-II RealDigital CPLD Design Kit contains everything you need to explore all the new capabilities of the CoolRunner-II RealDigital CPLD. With this kit, you will be able to do everything necessary to test your designs in the industry’s best 1.8V CPLD.

For low-power/high-speed designs, a 256 macrocell CoolRunner-II device in a 144-pin thin quad flat pack (TQ144) package is included with every kit. If you need more programmable logic or want to try a different Xilinx CPLD, an additional socket accepts a CoolRunner-II 64 or 32 macrocell device for other low-power/high-speed designs. Want to test run a 2.5V or 3.3V Xilinx CPLD? This socket also accepts Xilinx best-selling XC9500XL or XC9500XV devices in 36 or 72 macrocell sizes.

The CoolRunner-II CPLD design kit board (Figure 1) can be powered either by a standard power supply or by two AA batteries (battery holder included). The kit also includes a parallel cable for programming your CPLD. The cable simply goes from your PC parallel port to the parallel port connection on the board.

To help you get started, we have included a Programmable Logic Quick Start Book that contains installation instructions for the ISE WebPACK™ software, as well as step-by-step instructions on how to use, enter, and synthesize designs, and how to target Xilinx programmable logic devices.

To give you a good jump-start on designing your own applications, we give you design examples in both schematic and high-level language, such as VHDL.

The kit comes with a resource CD that contains a great deal of useful information:

• Reference designs in VHDL, user constraint file (UCF), and HDL design files
• Instructional video demonstrating the entire process, from design to programming of the device
• ISE WebPACK overview and software options for different Xilinx devices
• Links to related websites
• Application notes, data sheets, power consumption comparison, product pages, articles, and other product presentations
• Technical presentations and packaging information
• Top 10 FAQs and where to find other answers to questions
• Product brochures, reference manuals, and product briefs
• Video featuring Xilinx CEO Wim Roelandts.

Or you might experiment with the other new memory device interfaces not supported on your current microprocessor. A breadboard area allows you to add components for use in future designs, and you can also connect a daughtercard to the CoolRunner-II design kit board via the dual inline headers.

Designers new to programmable logic can use the demo board with its tutorial to quickly get up to speed on tool usage. The demo covers all aspects of designing a CPLD, from design entry with WebPACK, through simulation, to production of a JEDEC file used to program the device. This straightforward tutorial should get you up and designing within hours, and can also be used to encourage lab technicians to explore their own design aspirations.

The demo board is handy to have in your lab to test new design ideas for implementation on current products. If your system already includes a CPLD, it serves as a nice test bed for running upgrade tests. If power is your concern, the CoolRunner-II development board is especially useful for running different designs to test power consumption. If you want some ideas about reducing power consumption, check out the low-power tips and tricks application note XAPP346 on the CLPD application notes webpage (www.xilinx.com/apps/epld.htm – see Table 1 for a list of all of the application notes described in this article).

Table 1 – All CoolRunner-II application notes can be found at www.xilinx.com/apps/epld.htm.

XAPP137	Configuring Virtex FPGAs from Parallel EPROMs with a CPLD
XAPP345	IrDA and UART Design in a CoolRunner CPLD
XAPP346	Low Power Tips for CoolRunner Design
XAPP349	CoolRunner CPLD 8051 Microcontroller Interface
XAPP380	Building Crosspoint Switches with CoolRunner-II CPLDs
XAPP387	PicoBlaze 8-Bit Microcontroller for CPLD Devices
XAPP388	"On the Fly" Reconfigurations

The 256-macrocell (XC2C256) CPLD in a TQ144 – with room for other devices – gives you a good sense of design capacity. With this device configuration you get 118 I/Os, two I/O banks, clock doubling/division, and voltage-referenced I/O. If you need voltage-level translation, this device can handle 1.5V, 1.8V, 2.5V, or 3.3V I/Os. If your design is relatively simple, try the 32 or 64 macrocell device. If your design is complex, try the 256 macrocell configuration. If you think partitioning your design offers the best solution, use both devices. This board is designed to give you the maximum amount of flexibility.

What Can You Do With It?
With both a breadboard area and dual inline header sockets, the design kit board is suitable for developing on-board applications, attaching daughtercard boards, or communicating with another board via headers. It is large enough to accept many useful designs, including standard bus protocols (SPI and I2C), microcontroller interfaces, and serial communications, such as Infrared Data Association and universal asynchronous receiver transmitter (UART) designs, which have already been created by Xilinx application engineers. These last items are available free by downloading application note XAPP345.

PicoBlaze Soft Processor
The CoolRunner-II design board is extremely useful for evaluating the PicoBlaze™ soft processor in your design. Available for downloading free from application note XAPP387, the PicoBlaze soft processor offers a constant K-coded programmable state machine, and is written in VHDL and C programming languages. Extremely customizable, both its size and functionality can easily be changed, making PicoBlaze an ideal application for content-sensitive designs. The PicoBlaze soft processor provides 49 different instructions, eight 8-bit registers, 256 directly addressable ports, and a maskable interrupt. If you simply want an 8-bit microcontroller interface, take a look at application note XAPP349.

Memory Interface
The CoolRunner-II design board may well be the best solution for testing new memory interfaces. With multiple memory interfaces – including HSTL, SSTL, and LVCMOS – you can test SDRAM, SSDRAM, MSDRAM (mobile SDRAM), UtRAM (UniTransistor RAM), cellular RAM, and flash memories. You can even design your own memory controller for new flavors of portable or mobile RAM as they become available.

The CPLD application notes webpage contains many memory design examples, including beginning designs for flash and DDR SDRAM memory. Check this website often for new memory interfaces and updates or to download an HDL design and get email notification of new application notes.

Crosspoint Switch
The non-blocking architecture allows each output to be independently connected to any input, and any input to be connected to any or all outputs. The double-row latch architecture utilized in this design allows switch reprogramming to occur in the background during operation. Activation of the new configuration occurs with a single configuration pulse. Each output can be individually disabled and set to a high-impedance state, allowing easy expansion to larger switch array sizes. This is covered in detail in application note XAPP380.

OTF Reconfiguration
On the fly (OTF) reconfiguration permits the CPLD to operate with an initial design pattern while simultaneously acquiring a second pattern. For example, your first design pattern can be a power-up application, such as a built-in self-test (BIST), and the second pattern can be one of normal device operation. If you want to run diagnostics on your system on power-up, you would load a functional pattern to perform additional bus interface support. The second pattern can be configured into the device with minimal disturbance to its operation.

Another important consideration is that OTF reconfiguration enhances security, because switching keys on the fly permits robust protocols for data communication designs that can be tough to crack. OTF reconfiguration takes in-system programming (ISP) to a new level and will undoubtedly spawn many new applications that take advantage of this capability. More information about OTF can be found in application note XAPP388.

FPGA Downloader
Another common use for CPLDs is as an FPGA downloader. At power-up the CPLD sequentially loads each FPGA with a pattern, which is stored in external memory. By assigning a CPLD to accomplish this task, you can get double duty from the CPLD. On power-up, it loads the FPGA; after this power-up task is done, you can OTF reconfigure the CPLD and use it as a functioning device in your design. It’s like getting two devices for the price of one. To learn more about this application, see application note XAPP137.

If you do experience problems, a website has been set up for you at www. digilentinc.com to help troubleshoot the board.

Conclusion
CoolRunner-II RealDigital CPLDs can be the perfect solution for any high-speed/low-power design and cover many application areas. In addition to their features, these devices also come in packages that suit high volume and small form factor packaging.

To order your CoolRunner-II RealDigital Design Kit, just go to www.xilinx.com/cpld/ and click on "CoolRunner-II Design Kit for $49.99."

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