The latest release of Xilinx programmable design software saves you time – and money.

The newest version of Xilinx Integrated Software Environment programmable design tools – ISE 6.1i – is now available to registered in-maintenance Xilinx customers.

This new release of our industry-leading programmable design suite continues the Xilinx commitment to lower your design costs, to deliver ease of use that focuses on solving your specific engineering problems, and to expand support for low-cost Spartan™-3 FPGAs – and native support for the Red Hat™ Linux™ operating system.

Some of the new capabilities in ISE 6.1i include:

• Support for the largest Spartan-3 XC3S4000 and XC3S5000 devices
• Increased Spartan-3 device support in ISE WebPACK™ and ISE BaseX
• New ISE native Linux support
• Automatic Web software update
• PACE (Pinout and Area Constraints Editor) enhancements for CPLD, and PC board design assistance
• Project Navigator mixed-language and embedded design enhancements
• As much as 15% better performance than ISE 5.1i.

More Spartan-3 Devices in ISE
ISE WebPACK 6.1i, which is free to designers, has added support for the Spartan-3 XC3S200 and XC3S400 devices, at 200,000 and 400,000 system gates, respectively. ISE BaseX now supports the XC3S400 device as well.

High Density Spartan-3 Support
ISE Foundation™ and ISE Alliance Series™ 6.1i versions support the highest-density Spartan-3 devices, the XC3S4000 and XC3S5000 FPGAs at 4 million and 5 million gates, respectively. Now you have even greater flexibility in choosing Spartan-3 devices and ISE configurations.

ISE Supports Native Linux
ISE 6.1i is also the first ISE release that runs on native Red Hat Linux versions 7.3 and 8.0. The installation CDs for 32-bit Linux that come with your ISE 6.1i shipment will help you make the best use of your corporate programmable design platforms.

Automatic Web Update
Another new capability is automatic Web software update. Upon execution, ISE will notify you whenever a new service pack upgrade is available. And if selected, ISE will only download those parts of the service pack that apply to your unique installation. This feature saves you the time of identifying and updating your current software configuration – and minimizing the required disk space.

Ease of Use Engineers Demand
Many software design companies settle for a good look-and-feel graphical user interface as their standard for “ease of use.” ISE 6.1i goes beyond being just another pretty GUI. It focuses on solving engineering bottlenecks and design headaches that hinder your design process and progress.

PACE Enhancements
Figure 1 shows an example of PACE (Pinout and Area Constraints Editor), introduced with ISE 5. PACE delivers pin definition and area management in an easy-to-use, graphically oriented environment. You can speed your design flow faster and easier with PACE.

PACE now offers CSV (comma separated value) file import and export. This capability offers you new flexibility in PC board design, including the ability to create pin tables in Microsoft™ Excel™ spreadsheets and import those into PACE. If the pin tables are modified, they can be exported back to the Excel workbook using the CSV format. This export/import capability eases the job of integrating the logic device into the board layout.

PACE can also import and export VHDL and Verilog™ HDL files, which allow PACE to define I/O from the HDL port definitions – or write top-level HDL starting templates.

New design check capabilities help you predict output problems. PACE contains a new package flight-time display that graphically shows pin-delay time that is based on pin-to-pad estimates. PACE also checks for simultaneous switched outputs to prevent common high-drive strength outputs that could potentially create ground bounce signal problems.

The new version of PACE also supports an enhanced auto-floorplanning capability, which lets you identify area groups using PACE. Once a logic area group is identified, the ISE place-and-route tools create the floorplan, which saves you more design time.

Expanded Project Navigator
Project Navigator, the ISE design and project manager, has also been enhanced in version 6.1i. Project Navigator now supports mixed-language Verilog and VHDL design for customers using Synplicity® Corp.’s Synplify® tool suite or XST (Xilinx Synthesis Technology) software for their synthesis solutions. This new flexibility allows managers to mix the best possible design source code for any particular project. This, in turn, allows you to more easily and quickly mix and match your purchased IP with your own in-house design expertise regardless of design language.

Project Navigator also now links to the Xilinx EDK (Embedded Design Kit) XPS project manager supporting MicroBlaze™ and Virtex-II Pro™ embedded processor designs. This new integration shows an embedded project entity along with the design logic, and launches XPS when double-clicked, offering the first in a new series of upcoming enhancements that will bring Xilinx logic and embedded programmable design tools closer together.

Still the Fastest
ISE 6.1i continues to deliver the fastest programmable device performance available. Enhancements to our lightning-quick ProActive Timing Closure implementation technology now deliver up to 15% better performance over ISE 5.1i software.

The new INPUT_JITTER timing constraint lets an engineer describe system jitter and clock edge uncertainty. With more timing constraints, high-speed design rules, and local clocking options than any other programmable vendor, ISE 6.1i gives you the ability to design high-speed memory interface timing and double-data-rate local clock designs accurately.

Conclusion
ISE continues to define the standard of logic design. By concentrating on cost, productivity, and ease of use, ISE is delivering the tools necessary for programmable systems design that helps you squeeze the most out of your logic device.

To find out more about ISE 6.1i, go to www.xilinx.com/xcell_ise/. To order your copy of ISE 6.1i, contact your local sales support representative.

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